2014-05-11 04:13:51 +02:00
|
|
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{
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"name": null,
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"sim_quantum": 0,
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"system": {
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2014-09-21 22:15:14 +02:00
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"kernel": "",
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2015-03-07 19:55:56 +01:00
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"mmap_using_noreserve": false,
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"kernel_addr_check": true,
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"membus": {
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"slave": {
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"peer": [
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"system.system_port",
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"system.l2c.mem_side"
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],
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"role": "SLAVE"
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},
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"name": "membus",
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"snoop_filter": null,
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"forward_latency": 4,
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"clk_domain": "system.clk_domain",
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"system": "system",
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"width": 16,
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"eventq_index": 0,
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"master": {
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"peer": [
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"system.physmem.port"
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],
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"role": "MASTER"
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},
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"response_latency": 2,
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"cxx_class": "CoherentXBar",
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"path": "system.membus",
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"snoop_response_latency": 4,
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"type": "CoherentXBar",
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"use_default_range": false,
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"frontend_latency": 3
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},
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"symbolfile": "",
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2014-05-11 04:13:51 +02:00
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"l2c": {
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2014-09-21 22:15:14 +02:00
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"is_top_level": false,
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"prefetcher": null,
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"clk_domain": "system.cpu_clk_domain",
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"write_buffers": 8,
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"response_latency": 20,
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"cxx_class": "BaseCache",
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"size": 4194304,
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2014-05-11 04:13:51 +02:00
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"tags": {
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"name": "tags",
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"eventq_index": 0,
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"hit_latency": 20,
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2014-09-21 22:15:14 +02:00
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"clk_domain": "system.cpu_clk_domain",
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2014-05-11 04:13:51 +02:00
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"sequential_access": false,
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"assoc": 8,
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"cxx_class": "LRU",
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"path": "system.l2c.tags",
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"block_size": 64,
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"type": "LRU",
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"size": 4194304
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},
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2014-09-21 22:15:14 +02:00
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"system": "system",
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2014-05-11 04:13:51 +02:00
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"max_miss_count": 0,
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"eventq_index": 0,
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2014-09-21 22:15:14 +02:00
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"mem_side": {
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"peer": "system.membus.slave[1]",
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"role": "MASTER"
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},
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"mshrs": 20,
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"forward_snoops": true,
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"hit_latency": 20,
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2015-03-07 19:55:56 +01:00
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"demand_mshr_reserve": 1,
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2014-09-21 22:15:14 +02:00
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"tgts_per_mshr": 12,
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"addr_ranges": [
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"0:18446744073709551615"
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],
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"assoc": 8,
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2014-05-11 04:13:51 +02:00
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"prefetch_on_access": false,
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"path": "system.l2c",
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2014-09-21 22:15:14 +02:00
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"name": "l2c",
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2014-05-11 04:13:51 +02:00
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"type": "BaseCache",
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2014-09-21 22:15:14 +02:00
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"sequential_access": false,
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"cpu_side": {
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"peer": "system.toL2Bus.master[0]",
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"role": "SLAVE"
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},
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"two_queue": false
|
2014-05-11 04:13:51 +02:00
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},
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2014-09-21 22:15:14 +02:00
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"readfile": "",
|
2014-05-11 04:13:51 +02:00
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"cxx_class": "System",
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"load_offset": 0,
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"work_end_ckpt_count": 0,
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2014-09-21 22:15:14 +02:00
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"memories": [
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"system.physmem"
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],
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2014-05-11 04:13:51 +02:00
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"work_begin_ckpt_count": 0,
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"clk_domain": {
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"name": "clk_domain",
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2014-09-21 22:15:14 +02:00
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|
|
"clock": [
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|
1000
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|
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],
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2014-09-01 23:55:52 +02:00
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"init_perf_level": 0,
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2014-09-21 22:15:14 +02:00
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"voltage_domain": "system.voltage_domain",
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2014-05-11 04:13:51 +02:00
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|
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"eventq_index": 0,
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"cxx_class": "SrcClockDomain",
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"path": "system.clk_domain",
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2014-09-01 23:55:52 +02:00
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|
|
"type": "SrcClockDomain",
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|
|
"domain_id": -1
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2014-05-11 04:13:51 +02:00
|
|
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},
|
2014-09-21 22:15:14 +02:00
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"mem_ranges": [],
|
2014-05-11 04:13:51 +02:00
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"eventq_index": 0,
|
2014-09-01 23:55:52 +02:00
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"dvfs_handler": {
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"enable": false,
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|
"name": "dvfs_handler",
|
2014-09-21 22:15:14 +02:00
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|
|
"sys_clk_domain": "system.clk_domain",
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|
|
|
"transition_latency": 100000000,
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2014-09-01 23:55:52 +02:00
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|
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"eventq_index": 0,
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"cxx_class": "DVFSHandler",
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2014-09-21 22:15:14 +02:00
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|
|
"domains": [],
|
2014-09-01 23:55:52 +02:00
|
|
|
"path": "system.dvfs_handler",
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|
|
|
"type": "DVFSHandler"
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|
|
|
},
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|
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"work_end_exit_count": 0,
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|
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"type": "System",
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|
|
|
"voltage_domain": {
|
2014-09-21 22:15:14 +02:00
|
|
|
"name": "voltage_domain",
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2014-09-01 23:55:52 +02:00
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
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"voltage": [
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|
|
|
"1.0"
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|
|
|
],
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|
|
|
"cxx_class": "VoltageDomain",
|
2014-09-01 23:55:52 +02:00
|
|
|
"path": "system.voltage_domain",
|
2014-09-21 22:15:14 +02:00
|
|
|
"type": "VoltageDomain"
|
2014-09-01 23:55:52 +02:00
|
|
|
},
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|
|
|
"cache_line_size": 64,
|
2014-09-21 22:15:14 +02:00
|
|
|
"boot_osflags": "a",
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|
|
|
"physmem": {
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|
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|
"range": "0:134217727",
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|
"latency": 30000,
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"name": "physmem",
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"eventq_index": 0,
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"clk_domain": "system.clk_domain",
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|
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|
"latency_var": 0,
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|
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|
"bandwidth": "73.000000",
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|
|
|
"conf_table_reported": true,
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|
|
|
"cxx_class": "SimpleMemory",
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|
|
|
"path": "system.physmem",
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|
|
|
"null": false,
|
|
|
|
"type": "SimpleMemory",
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|
|
|
"port": {
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|
|
|
"peer": "system.membus.master[0]",
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|
|
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"role": "SLAVE"
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|
|
|
},
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|
|
"in_addr_map": true
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|
|
|
},
|
2014-09-01 23:55:52 +02:00
|
|
|
"work_cpus_ckpt_count": 0,
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"work_begin_exit_count": 0,
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|
|
|
"path": "system",
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|
|
|
"cpu_clk_domain": {
|
|
|
|
"name": "cpu_clk_domain",
|
2014-09-21 22:15:14 +02:00
|
|
|
"clock": [
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|
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|
500
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|
|
|
],
|
2014-09-01 23:55:52 +02:00
|
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|
"init_perf_level": 0,
|
2014-09-21 22:15:14 +02:00
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|
|
"voltage_domain": "system.voltage_domain",
|
2014-09-01 23:55:52 +02:00
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|
|
"eventq_index": 0,
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|
"cxx_class": "SrcClockDomain",
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|
|
|
"path": "system.cpu_clk_domain",
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|
|
|
"type": "SrcClockDomain",
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|
|
|
"domain_id": -1
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|
|
|
},
|
2014-05-11 04:13:51 +02:00
|
|
|
"toL2Bus": {
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|
|
|
"slave": {
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|
|
|
"peer": [
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|
|
|
"system.cpu0.icache.mem_side",
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|
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|
"system.cpu0.dcache.mem_side",
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|
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|
"system.cpu1.icache.mem_side",
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|
|
|
"system.cpu1.dcache.mem_side",
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|
|
|
"system.cpu2.icache.mem_side",
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|
|
|
"system.cpu2.dcache.mem_side",
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|
|
"system.cpu3.icache.mem_side",
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|
|
"system.cpu3.dcache.mem_side"
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|
|
|
],
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|
|
|
"role": "SLAVE"
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|
|
|
},
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|
|
|
"name": "toL2Bus",
|
2014-09-21 22:15:14 +02:00
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|
|
"snoop_filter": null,
|
2015-03-07 19:55:56 +01:00
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|
|
"forward_latency": 0,
|
2014-09-21 22:15:14 +02:00
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|
|
"clk_domain": "system.cpu_clk_domain",
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|
|
|
"system": "system",
|
2015-03-07 19:55:56 +01:00
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|
|
"width": 32,
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
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"master": {
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"peer": [
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|
"system.l2c.cpu_side"
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],
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|
"role": "MASTER"
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|
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|
},
|
2015-03-07 19:55:56 +01:00
|
|
|
"response_latency": 1,
|
2014-09-21 22:15:14 +02:00
|
|
|
"cxx_class": "CoherentXBar",
|
2014-05-11 04:13:51 +02:00
|
|
|
"path": "system.toL2Bus",
|
2015-03-07 19:55:56 +01:00
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|
|
"snoop_response_latency": 1,
|
2014-09-21 22:15:14 +02:00
|
|
|
"type": "CoherentXBar",
|
2015-03-07 19:55:56 +01:00
|
|
|
"use_default_range": false,
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|
|
|
"frontend_latency": 1
|
2014-05-11 04:13:51 +02:00
|
|
|
},
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|
|
|
"mem_mode": "timing",
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|
|
|
"name": "system",
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|
|
|
"init_param": 0,
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|
|
|
"system_port": {
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|
|
|
"peer": "system.membus.slave[0]",
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|
|
|
"role": "MASTER"
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|
|
|
},
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|
|
|
"load_addr_mask": 1099511627775,
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|
|
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"cpu": [
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|
|
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{
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|
|
|
"do_statistics_insts": true,
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"numThreads": 1,
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|
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"itb": {
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|
|
|
"name": "itb",
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|
|
|
"eventq_index": 0,
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|
|
|
"cxx_class": "AlphaISA::TLB",
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|
|
|
"path": "system.cpu0.itb",
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|
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|
"type": "AlphaTLB",
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|
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|
"size": 48
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|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
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|
|
|
"function_trace": false,
|
2014-05-11 04:13:51 +02:00
|
|
|
"do_checkpoint_insts": true,
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|
|
|
"cxx_class": "TimingSimpleCPU",
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|
|
|
"max_loads_all_threads": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"function_trace_start": 0,
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|
|
|
"cpu_id": 0,
|
2014-09-21 22:15:14 +02:00
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|
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"checker": null,
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
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|
|
|
"do_quiesce": true,
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|
|
|
"type": "TimingSimpleCPU",
|
2014-09-21 22:15:14 +02:00
|
|
|
"profile": 0,
|
2014-05-11 04:13:51 +02:00
|
|
|
"icache_port": {
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|
|
|
"peer": "system.cpu0.icache.cpu_side",
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|
|
|
"role": "MASTER"
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|
|
|
},
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|
|
|
"icache": {
|
2014-09-21 22:15:14 +02:00
|
|
|
"is_top_level": true,
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|
|
|
"prefetcher": null,
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|
|
|
"clk_domain": "system.cpu_clk_domain",
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|
|
|
"write_buffers": 8,
|
|
|
|
"response_latency": 2,
|
|
|
|
"cxx_class": "BaseCache",
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|
|
|
"size": 32768,
|
2014-05-11 04:13:51 +02:00
|
|
|
"tags": {
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|
|
"name": "tags",
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|
|
|
"eventq_index": 0,
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|
|
|
"hit_latency": 2,
|
2014-09-21 22:15:14 +02:00
|
|
|
"clk_domain": "system.cpu_clk_domain",
|
2014-05-11 04:13:51 +02:00
|
|
|
"sequential_access": false,
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|
|
|
"assoc": 1,
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|
|
|
"cxx_class": "LRU",
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|
|
|
"path": "system.cpu0.icache.tags",
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|
|
|
"block_size": 64,
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|
|
|
"type": "LRU",
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|
|
|
"size": 32768
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|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
2014-05-11 04:13:51 +02:00
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|
|
"max_miss_count": 0,
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|
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|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"mem_side": {
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|
|
|
"peer": "system.toL2Bus.slave[0]",
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|
|
|
"role": "MASTER"
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|
|
|
},
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|
|
|
"mshrs": 4,
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|
|
|
"forward_snoops": true,
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|
|
|
"hit_latency": 2,
|
2015-03-07 19:55:56 +01:00
|
|
|
"demand_mshr_reserve": 1,
|
2014-09-21 22:15:14 +02:00
|
|
|
"tgts_per_mshr": 20,
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|
|
|
"addr_ranges": [
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|
|
|
"0:18446744073709551615"
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|
|
|
],
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|
|
|
"assoc": 1,
|
2014-05-11 04:13:51 +02:00
|
|
|
"prefetch_on_access": false,
|
|
|
|
"path": "system.cpu0.icache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"name": "icache",
|
2014-05-11 04:13:51 +02:00
|
|
|
"type": "BaseCache",
|
2014-09-21 22:15:14 +02:00
|
|
|
"sequential_access": false,
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|
|
|
"cpu_side": {
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|
|
|
"peer": "system.cpu0.icache_port",
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|
|
|
"role": "SLAVE"
|
|
|
|
},
|
|
|
|
"two_queue": false
|
2014-05-11 04:13:51 +02:00
|
|
|
},
|
|
|
|
"interrupts": {
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|
|
|
"eventq_index": 0,
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|
|
|
"path": "system.cpu0.interrupts",
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|
|
|
"type": "AlphaInterrupts",
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|
|
|
"name": "interrupts",
|
|
|
|
"cxx_class": "AlphaISA::Interrupts"
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"dcache_port": {
|
|
|
|
"peer": "system.cpu0.dcache.cpu_side",
|
|
|
|
"role": "MASTER"
|
|
|
|
},
|
2014-05-11 04:13:51 +02:00
|
|
|
"socket_id": 0,
|
|
|
|
"max_insts_all_threads": 0,
|
|
|
|
"path": "system.cpu0",
|
2014-09-21 22:15:14 +02:00
|
|
|
"max_loads_any_thread": 0,
|
2014-05-11 04:13:51 +02:00
|
|
|
"switched_out": false,
|
|
|
|
"workload": [
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|
|
|
{
|
|
|
|
"name": "workload",
|
2014-09-21 22:15:14 +02:00
|
|
|
"output": "cout",
|
|
|
|
"chkpt": "",
|
|
|
|
"errout": "cerr",
|
2015-03-07 19:55:56 +01:00
|
|
|
"kvmInSE": false,
|
2014-09-21 22:15:14 +02:00
|
|
|
"system": "system",
|
|
|
|
"useArchPT": false,
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
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2014-09-21 22:15:14 +02:00
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"file": "/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz",
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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|
2014-05-11 04:13:51 +02:00
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}
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],
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2015-03-07 19:55:56 +01:00
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2014-09-21 22:15:14 +02:00
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},
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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{
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"type": "AlphaISA"
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}
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2014-05-11 04:13:51 +02:00
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{
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"path": "system.cpu1.itb",
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"type": "AlphaTLB",
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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"type": "TimingSimpleCPU",
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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"icache_port": {
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"peer": "system.cpu1.icache.cpu_side",
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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"path": "system.cpu1.icache.tags",
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2015-03-07 19:55:56 +01:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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"path": "system.cpu1.icache",
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2014-09-21 22:15:14 +02:00
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"name": "icache",
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2014-05-11 04:13:51 +02:00
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"type": "BaseCache",
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2014-09-21 22:15:14 +02:00
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"peer": "system.cpu1.icache_port",
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"role": "SLAVE"
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},
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2014-05-11 04:13:51 +02:00
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},
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"path": "system.cpu1.interrupts",
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"type": "AlphaInterrupts",
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"name": "interrupts",
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"cxx_class": "AlphaISA::Interrupts"
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},
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2014-09-21 22:15:14 +02:00
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"peer": "system.cpu1.dcache.cpu_side",
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},
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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{
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"name": "workload",
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2014-09-21 22:15:14 +02:00
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"output": "cout",
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"chkpt": "",
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"errout": "cerr",
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2015-03-07 19:55:56 +01:00
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2014-09-21 22:15:14 +02:00
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"system": "system",
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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"file": "/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz",
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2014-05-11 04:13:51 +02:00
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"cxx_class": "EioProcess",
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"path": "system.cpu1.workload",
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2014-09-21 22:15:14 +02:00
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"type": "EioProcess",
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"input": "None"
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2014-05-11 04:13:51 +02:00
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}
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],
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"name": "cpu1",
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},
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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"path": "system.cpu1.dcache.tags",
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},
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2015-03-07 19:55:56 +01:00
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2014-09-21 22:15:14 +02:00
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"role": "SLAVE"
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},
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2014-05-11 04:13:51 +02:00
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},
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2014-09-21 22:15:14 +02:00
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"isa": [
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{
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"type": "AlphaISA"
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}
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2014-05-11 04:13:51 +02:00
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}
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},
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{
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},
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
|
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2014-05-11 04:13:51 +02:00
|
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"icache_port": {
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"peer": "system.cpu2.icache.cpu_side",
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"role": "MASTER"
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|
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},
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2014-09-21 22:15:14 +02:00
|
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2014-05-11 04:13:51 +02:00
|
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2014-09-21 22:15:14 +02:00
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"clk_domain": "system.cpu_clk_domain",
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2014-05-11 04:13:51 +02:00
|
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"path": "system.cpu2.icache.tags",
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2014-09-21 22:15:14 +02:00
|
|
|
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2015-03-07 19:55:56 +01:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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"peer": "system.cpu2.dcache.cpu_side",
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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{
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2014-09-21 22:15:14 +02:00
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"output": "cout",
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2015-03-07 19:55:56 +01:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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}
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],
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2015-03-07 19:55:56 +01:00
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2014-09-21 22:15:14 +02:00
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"peer": "system.cpu2.dcache_port",
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},
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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{
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"type": "AlphaISA"
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}
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2014-05-11 04:13:51 +02:00
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{
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"path": "system.cpu3.itb",
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"type": "AlphaTLB",
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},
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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"peer": "system.cpu3.icache.cpu_side",
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2015-03-07 19:55:56 +01:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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},
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"name": "interrupts",
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"cxx_class": "AlphaISA::Interrupts"
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},
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2014-09-21 22:15:14 +02:00
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"peer": "system.cpu3.dcache.cpu_side",
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},
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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{
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2014-09-21 22:15:14 +02:00
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"output": "cout",
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"errout": "cerr",
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2015-03-07 19:55:56 +01:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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"file": "/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz",
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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"type": "EioProcess",
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2014-05-11 04:13:51 +02:00
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}
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],
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"path": "system.cpu3.dtb",
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2015-03-07 19:55:56 +01:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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2014-09-21 22:15:14 +02:00
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2014-05-11 04:13:51 +02:00
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"type": "ExeTracer",
|
|
|
|
"name": "tracer",
|
|
|
|
"cxx_class": "Trace::ExeTracer"
|
|
|
|
}
|
|
|
|
}
|
|
|
|
],
|
2014-09-21 22:15:14 +02:00
|
|
|
"num_work_ids": 16,
|
|
|
|
"work_item_id": -1,
|
2014-05-11 04:13:51 +02:00
|
|
|
"work_begin_cpu_id_exit": -1
|
|
|
|
},
|
2014-09-21 22:15:14 +02:00
|
|
|
"time_sync_period": 100000000000,
|
2014-05-11 04:13:51 +02:00
|
|
|
"eventq_index": 0,
|
2014-09-21 22:15:14 +02:00
|
|
|
"time_sync_spin_threshold": 100000000,
|
2014-05-11 04:13:51 +02:00
|
|
|
"cxx_class": "Root",
|
|
|
|
"path": "root",
|
|
|
|
"time_sync_enable": false,
|
|
|
|
"type": "Root",
|
|
|
|
"full_system": false
|
|
|
|
}
|