2005-08-15 22:59:58 +02:00
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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2006-11-06 22:24:25 +01:00
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* Authors: Ali Saidi
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2005-08-15 22:59:58 +02:00
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*/
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/** @file
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* Isa Fake Device implementation
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*/
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#include "base/trace.hh"
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2006-04-11 19:42:47 +02:00
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#include "dev/isa_fake.hh"
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#include "mem/packet.hh"
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2006-10-20 08:38:45 +02:00
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#include "mem/packet_access.hh"
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2005-08-15 22:59:58 +02:00
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#include "sim/system.hh"
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using namespace std;
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2006-04-10 20:14:06 +02:00
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IsaFake::IsaFake(Params *p)
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: BasicPioDevice(p)
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2005-08-15 22:59:58 +02:00
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{
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2007-07-24 06:51:38 +02:00
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if (!p->ret_bad_addr)
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2006-11-06 22:24:25 +01:00
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pioSize = p->pio_size;
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2005-08-15 22:59:58 +02:00
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2007-07-24 06:51:38 +02:00
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retData8 = p->ret_data8;
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retData16 = p->ret_data16;
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retData32 = p->ret_data32;
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retData64 = p->ret_data64;
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2006-11-02 21:18:35 +01:00
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}
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Tick
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2006-11-06 22:24:25 +01:00
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IsaFake::read(PacketPtr pkt)
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2006-11-02 21:18:35 +01:00
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{
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2006-11-06 22:24:25 +01:00
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2007-08-27 06:45:40 +02:00
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pkt->makeAtomicResponse();
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2007-07-24 06:51:38 +02:00
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if (params()->warn_access != "")
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2006-12-04 06:54:40 +01:00
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warn("Device %s accessed by read to address %#x size=%d\n",
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name(), pkt->getAddr(), pkt->getSize());
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2007-07-24 06:51:38 +02:00
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if (params()->ret_bad_addr) {
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2007-10-31 06:21:54 +01:00
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DPRINTF(IsaFake, "read to bad address va=%#x size=%d\n",
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2006-11-06 22:24:25 +01:00
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pkt->getAddr(), pkt->getSize());
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2007-06-30 19:16:18 +02:00
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pkt->setBadAddress();
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2006-11-06 22:24:25 +01:00
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} else {
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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2007-10-31 06:21:54 +01:00
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DPRINTF(IsaFake, "read va=%#x size=%d\n",
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2006-11-06 22:24:25 +01:00
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pkt->getAddr(), pkt->getSize());
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switch (pkt->getSize()) {
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case sizeof(uint64_t):
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2006-12-04 06:54:40 +01:00
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pkt->set(retData64);
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2006-11-06 22:24:25 +01:00
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break;
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case sizeof(uint32_t):
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2006-12-04 06:54:40 +01:00
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pkt->set(retData32);
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2006-11-06 22:24:25 +01:00
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break;
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case sizeof(uint16_t):
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2006-12-04 06:54:40 +01:00
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pkt->set(retData16);
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2006-11-06 22:24:25 +01:00
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break;
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case sizeof(uint8_t):
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2006-12-04 06:54:40 +01:00
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pkt->set(retData8);
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2006-11-06 22:24:25 +01:00
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break;
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default:
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panic("invalid access size!\n");
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}
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}
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2006-11-02 21:18:35 +01:00
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return pioDelay;
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}
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Tick
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2006-11-06 22:24:25 +01:00
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IsaFake::write(PacketPtr pkt)
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2006-11-02 21:18:35 +01:00
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{
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2007-08-27 06:45:40 +02:00
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pkt->makeAtomicResponse();
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2007-07-24 06:51:38 +02:00
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if (params()->warn_access != "") {
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2006-12-04 06:54:40 +01:00
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uint64_t data;
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switch (pkt->getSize()) {
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case sizeof(uint64_t):
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data = pkt->get<uint64_t>();
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break;
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case sizeof(uint32_t):
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data = pkt->get<uint32_t>();
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break;
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case sizeof(uint16_t):
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data = pkt->get<uint16_t>();
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break;
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case sizeof(uint8_t):
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data = pkt->get<uint8_t>();
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break;
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default:
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panic("invalid access size!\n");
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}
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warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
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name(), pkt->getAddr(), pkt->getSize(), data);
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}
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2007-07-24 06:51:38 +02:00
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if (params()->ret_bad_addr) {
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2007-10-31 06:21:54 +01:00
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DPRINTF(IsaFake, "write to bad address va=%#x size=%d \n",
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2006-11-06 22:24:25 +01:00
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pkt->getAddr(), pkt->getSize());
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2007-06-30 19:16:18 +02:00
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pkt->setBadAddress();
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2006-11-06 22:24:25 +01:00
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} else {
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2007-10-31 06:21:54 +01:00
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DPRINTF(IsaFake, "write - va=%#x size=%d \n",
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2006-11-06 22:24:25 +01:00
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pkt->getAddr(), pkt->getSize());
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2006-12-04 06:54:40 +01:00
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2007-07-24 06:51:38 +02:00
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if (params()->update_data) {
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2006-12-04 06:54:40 +01:00
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switch (pkt->getSize()) {
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case sizeof(uint64_t):
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retData64 = pkt->get<uint64_t>();
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break;
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case sizeof(uint32_t):
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retData32 = pkt->get<uint32_t>();
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break;
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case sizeof(uint16_t):
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retData16 = pkt->get<uint16_t>();
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break;
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case sizeof(uint8_t):
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retData8 = pkt->get<uint8_t>();
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break;
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default:
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panic("invalid access size!\n");
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}
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}
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2006-11-06 22:24:25 +01:00
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}
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2006-11-02 21:18:35 +01:00
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return pioDelay;
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}
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2007-07-24 06:51:38 +02:00
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IsaFake *
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IsaFakeParams::create()
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2005-08-15 22:59:58 +02:00
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{
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2007-07-24 06:51:38 +02:00
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return new IsaFake(this);
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2005-08-15 22:59:58 +02:00
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}
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