gem5/dev/tsunami_pchip.cc

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/*
* Copyright (c) 2004 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* @file
* Tsunami PChip (pci)
*/
#include <deque>
#include <string>
#include <vector>
#include "base/trace.hh"
#include "dev/tsunami_pchip.hh"
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
#include "mem/bus/bus.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
#include "mem/functional_mem/memory_control.hh"
#include "mem/functional_mem/physical_memory.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
MemoryController *mmu, HierParams *hier,
Bus *bus, Tick pio_latency)
New and improved configuration mechanism. No more writing of wierd ini files. The ini files are still used as an intermediate step, but a sophisticated python library exists to help build them more easily. SConscript: add the new embedded file stuff remove all of the old object description junk base/inifile.cc: base/inifile.hh: get rid of findDefault and findAppend since they were the source of much evil. base/trace.cc: For now, if we don't have the dprintf_stream set up, dump to standard out. We probably want a command line option for this. dev/alpha_console.cc: PioDevice now takes a platform parameter. All PioDevices must have a pio_latency parameter. We stick a dummy parameter in here for now until we get rid of the builder stuff. dev/alpha_console.hh: don't need Platform anymore dev/baddev.cc: PioDevice now takes a platform parameter. All PioDevices must have a pio_latency parameter. We stick a dummy parameter in here for now until we get rid of the builder stuff. Same for the platform parameter, though we just pass the PioDevice a null parameter since it isn't used by this device and it's quicker. dev/baddev.hh: fix #include guards dev/etherlink.cc: rename parameters. dev/ethertap.cc: rename parameters dev/ide_ctrl.cc: All devices need an address even if it will get overwritten later. dev/ide_disk.cc: use an enum for the drive ID stuff. rename disk_delay -> delay Actually, I think that we should implement "cable select" and have the controller tell the drive what it is. dev/io_device.cc: dev/io_device.hh: All IO devices take a Platform * dev/ns_gige.cc: all devices need an io_bus. rename header_bus to io_bus We don't need stuff for the interrupt controller since it's all in the platform now. dev/ns_gige.hh: We don't need stuff for the interrupt controller now since it's all in the platform. dev/pciconfigall.cc: Pass a dummy NULL to the PioDevice for the platform since we don't need one. dev/pcidev.cc: Move a bunch of common functionality into the PciDev dev/platform.hh: remove unneeded code dev/tsunami.cc: remove unused param dev/tsunami_cchip.cc: pass platform pointer dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart.cc: pass platform variable dev/uart.hh: don't need to keep a platform pointer. it's in the base class kern/linux/linux_system.cc: kern/tru64/tru64_system.cc: rename some parameters sim/builder.cc: clean up builder code. use more parameters from the config node. all sections with a type= are now created, the old mechanisms no longer work sim/builder.hh: remove some extra variables since they are found in the ConfigNode sim/main.cc: add a quick hack command line argument -X to dump out the embedded files. (probably should be fixed up a little.) accept .mpy files printing to the streams has to happen after the hierarchy is built since we're moving away from param contexts sim/param.cc: add parsing support for ranges sim/process.cc: isValid isn't very useful anymore. interpret the names stdout, stderr, cout, cerr for the file descriptors sim/pyconfig/SConscript: Add Action handlers for creating an embedded python file and for creating an embedded C file. use these action handlers to embed all objects found in the objects tree into the binary along with the importer and the m5config stuff sim/pyconfig/m5config.py: Major changes to the original configuration file generator. These changes largely involve implementing copy-on-write like semantics for all of the SimObjects. Real documentation must be written. sim/universe.cc: Universe becomes a SimObject since we don't really have the notion of param contexts in the python code. --HG-- rename : sim/pyconfig/m5configbase.py => sim/pyconfig/m5config.py extra : convert_revision : c353453e5beb91c37f15755998fc0d8858c6829a
2005-01-15 10:12:25 +01:00
: PioDevice(name, t), addr(a), tsunami(t)
{
mmu->add_child(this, RangeSize(addr, size));
for (int i = 0; i < 4; i++) {
wsba[i] = 0;
wsm[i] = 0;
tba[i] = 0;
}
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&TsunamiPChip::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRate;
}
// initialize pchip control register
pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
//Set back pointer in tsunami
tsunami->pchip = this;
}
Fault
TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n",
req->vaddr, req->size);
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
switch (req->size) {
case sizeof(uint64_t):
switch(daddr) {
case TSDEV_PC_WSBA0:
*(uint64_t*)data = wsba[0];
return No_Fault;
case TSDEV_PC_WSBA1:
*(uint64_t*)data = wsba[1];
return No_Fault;
case TSDEV_PC_WSBA2:
*(uint64_t*)data = wsba[2];
return No_Fault;
case TSDEV_PC_WSBA3:
*(uint64_t*)data = wsba[3];
return No_Fault;
case TSDEV_PC_WSM0:
*(uint64_t*)data = wsm[0];
return No_Fault;
case TSDEV_PC_WSM1:
*(uint64_t*)data = wsm[1];
return No_Fault;
case TSDEV_PC_WSM2:
*(uint64_t*)data = wsm[2];
return No_Fault;
case TSDEV_PC_WSM3:
*(uint64_t*)data = wsm[3];
return No_Fault;
case TSDEV_PC_TBA0:
*(uint64_t*)data = tba[0];
return No_Fault;
case TSDEV_PC_TBA1:
*(uint64_t*)data = tba[1];
return No_Fault;
case TSDEV_PC_TBA2:
*(uint64_t*)data = tba[2];
return No_Fault;
case TSDEV_PC_TBA3:
*(uint64_t*)data = tba[3];
return No_Fault;
case TSDEV_PC_PCTL:
*(uint64_t*)data = pctl;
return No_Fault;
case TSDEV_PC_PLAT:
panic("PC_PLAT not implemented\n");
case TSDEV_PC_RES:
panic("PC_RES not implemented\n");
case TSDEV_PC_PERROR:
*(uint64_t*)data = 0x00;
return No_Fault;
case TSDEV_PC_PERRMASK:
*(uint64_t*)data = 0x00;
return No_Fault;
case TSDEV_PC_PERRSET:
panic("PC_PERRSET not implemented\n");
case TSDEV_PC_TLBIV:
panic("PC_TLBIV not implemented\n");
case TSDEV_PC_TLBIA:
*(uint64_t*)data = 0x00; // shouldn't be readable, but linux
return No_Fault;
case TSDEV_PC_PMONCTL:
panic("PC_PMONCTL not implemented\n");
case TSDEV_PC_PMONCNT:
panic("PC_PMONCTN not implemented\n");
default:
panic("Default in PChip Read reached reading 0x%x\n", daddr);
} // uint64_t
break;
case sizeof(uint32_t):
case sizeof(uint16_t):
case sizeof(uint8_t):
default:
panic("invalid access size(?) for tsunami register!\n\n");
}
DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
return No_Fault;
}
Fault
TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
req->vaddr, req->size);
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
switch (req->size) {
case sizeof(uint64_t):
switch(daddr) {
case TSDEV_PC_WSBA0:
wsba[0] = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_WSBA1:
wsba[1] = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_WSBA2:
wsba[2] = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_WSBA3:
wsba[3] = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_WSM0:
wsm[0] = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_WSM1:
wsm[1] = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_WSM2:
wsm[2] = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_WSM3:
wsm[3] = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_TBA0:
tba[0] = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_TBA1:
tba[1] = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_TBA2:
tba[2] = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_TBA3:
tba[3] = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_PCTL:
pctl = *(uint64_t*)data;
return No_Fault;
case TSDEV_PC_PLAT:
panic("PC_PLAT not implemented\n");
case TSDEV_PC_RES:
panic("PC_RES not implemented\n");
case TSDEV_PC_PERROR:
return No_Fault;
case TSDEV_PC_PERRMASK:
panic("PC_PERRMASK not implemented\n");
case TSDEV_PC_PERRSET:
panic("PC_PERRSET not implemented\n");
case TSDEV_PC_TLBIV:
panic("PC_TLBIV not implemented\n");
case TSDEV_PC_TLBIA:
return No_Fault; // value ignored, supposted to invalidate SG TLB
case TSDEV_PC_PMONCTL:
panic("PC_PMONCTL not implemented\n");
case TSDEV_PC_PMONCNT:
panic("PC_PMONCTN not implemented\n");
default:
panic("Default in PChip Read reached reading 0x%x\n", daddr);
} // uint64_t
break;
case sizeof(uint32_t):
case sizeof(uint16_t):
case sizeof(uint8_t):
default:
panic("invalid access size(?) for tsunami register!\n\n");
}
DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
return No_Fault;
}
#define DMA_ADDR_MASK ULL(0x3ffffffff)
Addr
TsunamiPChip::translatePciToDma(Addr busAddr)
{
// compare the address to the window base registers
uint64_t tbaMask = 0;
uint64_t baMask = 0;
uint64_t windowMask = 0;
uint64_t windowBase = 0;
uint64_t pteEntry = 0;
Addr pteAddr;
Addr dmaAddr;
#if 0
DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr);
for (int i = 0; i < 4; i++) {
DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n",
i, wsba[i], wsm[i]);
windowBase = wsba[i];
windowMask = ~wsm[i] & (ULL(0xfff) << 20);
if ((busAddr & windowMask) == (windowBase & windowMask)) {
DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
i, windowBase, windowMask, (busAddr & windowMask),
(windowBase & windowMask));
}
}
#endif
for (int i = 0; i < 4; i++) {
windowBase = wsba[i];
windowMask = ~wsm[i] & (ULL(0xfff) << 20);
if ((busAddr & windowMask) == (windowBase & windowMask)) {
if (wsba[i] & 0x1) { // see if enabled
if (wsba[i] & 0x2) { // see if SG bit is set
/** @todo
This currently is faked by just doing a direct
read from memory, however, to be realistic, this
needs to actually do a bus transaction. The process
is explained in the tsunami documentation on page
10-12 and basically munges the address to look up a
PTE from a table in memory and then uses that mapping
to create an address for the SG page
*/
tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
memcpy((void *)&pteEntry,
tsunami->system->
physmem->dma_addr(pteAddr, sizeof(uint64_t)),
sizeof(uint64_t));
dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff));
} else {
baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff);
tbaMask = ~baMask;
dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask);
}
return (dmaAddr & DMA_ADDR_MASK);
}
}
}
// if no match was found, then return the original address
return busAddr;
}
void
TsunamiPChip::serialize(std::ostream &os)
{
SERIALIZE_SCALAR(pctl);
SERIALIZE_ARRAY(wsba, 4);
SERIALIZE_ARRAY(wsm, 4);
SERIALIZE_ARRAY(tba, 4);
}
void
TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_SCALAR(pctl);
UNSERIALIZE_ARRAY(wsba, 4);
UNSERIALIZE_ARRAY(wsm, 4);
UNSERIALIZE_ARRAY(tba, 4);
}
Tick
TsunamiPChip::cacheAccess(MemReqPtr &req)
{
return curTick + pioLatency;
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
SimObjectParam<Tsunami *> tsunami;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
SimObjectParam<Bus*> io_bus;
Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
INIT_PARAM(tsunami, "Tsunami"),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
CREATE_SIM_OBJECT(TsunamiPChip)
{
return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier,
io_bus, pio_latency);
}
REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)