2011-04-25 23:18:08 +02:00
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---------- Begin Simulation Statistics ----------
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2011-11-18 05:53:56 +01:00
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sim_seconds 0.494094 # Number of seconds simulated
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sim_ticks 494093841000 # Number of ticks simulated
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2011-04-25 23:18:08 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-11-18 05:53:56 +01:00
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host_inst_rate 111156 # Simulator instruction rate (inst/s)
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host_tick_rate 35920075 # Simulator tick rate (ticks/s)
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host_mem_usage 281020 # Number of bytes of host memory used
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host_seconds 13755.37 # Real time elapsed on the host
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2011-04-25 23:18:08 +02:00
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sim_insts 1528988756 # Number of instructions simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.workload.num_syscalls 551 # Number of system calls
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2011-11-18 05:53:56 +01:00
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system.cpu.numCycles 988187683 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-11-18 05:53:56 +01:00
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system.cpu.BPredUnit.lookups 245753731 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 245753731 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 16579058 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 236460078 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 218454939 # Number of BTB hits
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2011-04-25 23:18:08 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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2011-11-18 05:53:56 +01:00
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system.cpu.fetch.icacheStallCycles 205538766 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 1343537923 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 245753731 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 218454939 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 436709904 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 120016352 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 218837683 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 33103 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 345399 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 194719765 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 4085375 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 964635983 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.598912 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.317298 # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-11-18 05:53:56 +01:00
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system.cpu.fetch.rateDist::0 531979476 55.15% 55.15% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 32383346 3.36% 58.51% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 38813168 4.02% 62.53% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 32534184 3.37% 65.90% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 21860326 2.27% 68.17% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 36455994 3.78% 71.95% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 49125826 5.09% 77.04% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 36953777 3.83% 80.87% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 184529886 19.13% 100.00% # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-11-18 05:53:56 +01:00
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system.cpu.fetch.rateDist::total 964635983 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.248691 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.359598 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 264568111 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 174813294 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 373028079 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 49055371 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 103171128 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 2446190376 # Number of instructions handled by decode
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2011-09-13 18:58:09 +02:00
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system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
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2011-11-18 05:53:56 +01:00
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system.cpu.rename.SquashCycles 103171128 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 301809231 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 40269862 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 9996 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 383504038 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 135871728 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 2393655047 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 2663 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 25553817 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 92121641 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 2227336205 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 5630423595 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 5630180918 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 242677 # Number of floating rename lookups
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2011-05-23 17:59:13 +02:00
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system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
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2011-11-18 05:53:56 +01:00
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system.cpu.rename.UndoneMaps 800037178 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 1323 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 1277 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 319257105 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 577954406 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 226554784 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 227345729 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 66055755 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 2286934263 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 9822 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 1922478378 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 1310077 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 755451043 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 1190251690 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 9269 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 964635983 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.992957 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.810982 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-11-18 05:53:56 +01:00
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system.cpu.iq.issued_per_cycle::0 283040019 29.34% 29.34% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 160280005 16.62% 45.96% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 162996180 16.90% 62.85% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 148777682 15.42% 78.28% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 109013815 11.30% 89.58% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 60046720 6.22% 95.80% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 30822079 3.20% 99.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 8624231 0.89% 99.89% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 1035252 0.11% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-11-18 05:53:56 +01:00
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system.cpu.iq.issued_per_cycle::total 964635983 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-11-18 05:53:56 +01:00
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system.cpu.iq.fu_full::IntAlu 2243375 14.67% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.67% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 9951583 65.07% 79.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 3098283 20.26% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-11-18 05:53:56 +01:00
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system.cpu.iq.FU_type_0::No_OpClass 2418078 0.13% 0.13% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 1274783906 66.31% 66.44% # Type of FU issued
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.44% # Type of FU issued
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2011-11-18 05:53:56 +01:00
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system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 66.44% # Type of FU issued
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued
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2011-11-18 05:53:56 +01:00
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system.cpu.iq.FU_type_0::MemRead 463737726 24.12% 90.56% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 181538665 9.44% 100.00% # Type of FU issued
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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2011-11-18 05:53:56 +01:00
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system.cpu.iq.FU_type_0::total 1922478378 # Type of FU issued
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|
|
system.cpu.iq.rate 1.945459 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 15293241 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.007955 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 4826191069 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 3042585561 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1874784055 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 4988 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 82956 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 1935351994 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 1547 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 158191943 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 193852246 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 372238 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 283888 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 77394965 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2343 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 34 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.iew.iewSquashCycles 103171128 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 9041820 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1420232 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 2286944085 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 1121311 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 577954406 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 226555150 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 6075 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 1022506 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 29752 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 283888 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 15692203 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 2347782 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 18039985 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 1889278448 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 454785721 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 33199930 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.iew.exec_refs 629316980 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 176731992 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 174531259 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.911862 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 1882655317 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 1874784158 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1440755706 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 2135030641 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.iew.wb_rate 1.897194 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.674817 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.commit.commitSquashedInsts 757965703 # The number of squashed insts skipped by commit
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.commit.branchMispredicts 16607079 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 861464855 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.774871 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.287572 # Number of insts commited each cycle
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 338524013 39.30% 39.30% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 210779915 24.47% 63.76% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 75257513 8.74% 72.50% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 92637954 10.75% 83.25% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 34058407 3.95% 87.21% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 27966548 3.25% 90.45% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 15953506 1.85% 92.31% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 12303443 1.43% 93.73% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 53983556 6.27% 100.00% # Number of insts commited each cycle
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 861464855 # Number of insts commited each cycle
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.count 1528988756 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 533262345 # Number of memory references committed
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.loads 384102160 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.branches 149758588 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.commit.bw_lim_events 53983556 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.rob.rob_reads 3094435758 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 4677260376 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 606046 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 23551700 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.cpi 0.646301 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.646301 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.547266 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.547266 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 3179235417 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 1744932190 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 109 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 3 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 1039364909 # number of misc regfile reads
|
|
|
|
|
system.cpu.icache.replacements 9996 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 975.733254 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 194489021 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 11497 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 16916.501783 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.icache.occ_blocks::0 975.733254 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.476432 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 194495909 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 194495909 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 194495909 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 223856 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 223856 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 223856 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 1547338000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 1547338000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 1547338000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 194719765 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 194719765 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 194719765 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 6912.202487 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 6912.202487 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 6912.202487 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.icache.writebacks 6 # number of writebacks
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 2117 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 2117 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 2117 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 221739 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 221739 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 221739 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 830917000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 830917000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 830917000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.001139 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.001139 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.001139 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3747.274949 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.dcache.replacements 2527207 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4087.569371 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 440821768 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 2531303 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 174.148163 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 2135798000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4087.569371 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.997942 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 292074612 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 147577545 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 439652157 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 439652157 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 3115587 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 1582656 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 4698243 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 4698243 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 51949082000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 37383634500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 89332716500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 89332716500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 295190199 # number of ReadReq accesses(hits+misses)
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.dcache.demand_accesses 444350400 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 444350400 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.010555 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.010610 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.010573 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.010573 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 16673.930787 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 23620.821265 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 19014.068983 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 19014.068983 # average overall miss latency
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 74500 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 18625 # average number of cycles each access was blocked
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.dcache.writebacks 2229206 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 1355757 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 609338 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 1965095 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1965095 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 1759830 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 973318 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 2733148 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 2733148 # number of overall MSHR misses
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 14896925000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 17174770000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 32071695000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 32071695000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005962 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006525 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.006151 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.006151 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8464.979572 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17645.589622 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.l2cache.replacements 574699 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 21595.701500 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 3193363 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 593876 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 5.377154 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 271431195000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 7794.557657 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 13801.143843 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.237871 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.421177 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 1432788 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 2229212 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits 1238 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 524381 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 1957169 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 1957169 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 338369 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 208965 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 247135 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 585504 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 585504 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 11556474000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 9921000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 8477435500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 20033909500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 20033909500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 1771157 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 2229212 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 210203 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 771516 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 2542673 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 2542673 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.191044 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.994110 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.320324 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.230271 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.230271 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34153.465595 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 47.476850 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34302.852692 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34216.520297 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34216.520297 # average overall miss latency
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.l2cache.writebacks 411193 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 338369 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 208965 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 247135 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 585504 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 585504 # number of overall MSHR misses
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 10496162500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6478082000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666148000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 18162310500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 18162310500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-11-18 05:53:56 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191044 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994110 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320324 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.230271 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.230271 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.870319 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.799177 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.082141 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-25 23:18:08 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
