2006-04-23 00:45:01 +02:00
|
|
|
/*
|
2006-05-23 22:57:14 +02:00
|
|
|
* Copyright (c) 2005-2006 The Regents of The University of Michigan
|
2006-04-23 00:45:01 +02:00
|
|
|
* All rights reserved.
|
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions are
|
|
|
|
* met: redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer;
|
|
|
|
* redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
* documentation and/or other materials provided with the distribution;
|
|
|
|
* neither the name of the copyright holders nor the names of its
|
|
|
|
* contributors may be used to endorse or promote products derived from
|
|
|
|
* this software without specific prior written permission.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include "arch/faults.hh"
|
|
|
|
#include "arch/isa_traits.hh"
|
|
|
|
#include "config/full_system.hh"
|
|
|
|
#include "cpu/ozone/dyn_inst.hh"
|
|
|
|
#include "kern/kernel_stats.hh"
|
|
|
|
|
|
|
|
using namespace TheISA;
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
OzoneDynInst<Impl>::OzoneDynInst(FullCPU *cpu)
|
|
|
|
: BaseDynInst<Impl>(0, 0, 0, 0, cpu)
|
|
|
|
{
|
Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
|
|
|
this->setResultReady();
|
2006-04-23 00:45:01 +02:00
|
|
|
|
|
|
|
initInstPtrs();
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
OzoneDynInst<Impl>::OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
|
|
|
|
InstSeqNum seq_num, FullCPU *cpu)
|
|
|
|
: BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
|
|
|
|
{
|
|
|
|
initInstPtrs();
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
OzoneDynInst<Impl>::OzoneDynInst(StaticInstPtr _staticInst)
|
|
|
|
: BaseDynInst<Impl>(_staticInst)
|
|
|
|
{
|
|
|
|
initInstPtrs();
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
OzoneDynInst<Impl>::~OzoneDynInst()
|
|
|
|
{
|
|
|
|
DPRINTF(BE, "[sn:%lli] destructor called\n", this->seqNum);
|
|
|
|
for (int i = 0; i < this->numSrcRegs(); ++i) {
|
|
|
|
srcInsts[i] = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (int i = 0; i < this->numDestRegs(); ++i) {
|
|
|
|
prevDestInst[i] = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
dependents.clear();
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
Fault
|
|
|
|
OzoneDynInst<Impl>::execute()
|
|
|
|
{
|
|
|
|
// @todo: Pretty convoluted way to avoid squashing from happening when using
|
|
|
|
// the XC during an instruction's execution (specifically for instructions
|
|
|
|
// that have sideeffects that use the XC). Fix this.
|
|
|
|
bool in_syscall = this->thread->inSyscall;
|
|
|
|
this->thread->inSyscall = true;
|
|
|
|
|
|
|
|
this->fault = this->staticInst->execute(this, this->traceData);
|
|
|
|
|
|
|
|
this->thread->inSyscall = in_syscall;
|
|
|
|
|
|
|
|
return this->fault;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
Fault
|
|
|
|
OzoneDynInst<Impl>::initiateAcc()
|
|
|
|
{
|
|
|
|
// @todo: Pretty convoluted way to avoid squashing from happening when using
|
|
|
|
// the XC during an instruction's execution (specifically for instructions
|
|
|
|
// that have sideeffects that use the XC). Fix this.
|
|
|
|
bool in_syscall = this->thread->inSyscall;
|
|
|
|
this->thread->inSyscall = true;
|
|
|
|
|
|
|
|
this->fault = this->staticInst->initiateAcc(this, this->traceData);
|
|
|
|
|
|
|
|
this->thread->inSyscall = in_syscall;
|
|
|
|
|
|
|
|
return this->fault;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
Fault
|
|
|
|
OzoneDynInst<Impl>::completeAcc()
|
|
|
|
{
|
|
|
|
if (this->isLoad()) {
|
|
|
|
this->fault = this->staticInst->completeAcc(this->req->data,
|
|
|
|
this,
|
|
|
|
this->traceData);
|
|
|
|
} else if (this->isStore()) {
|
|
|
|
this->fault = this->staticInst->completeAcc((uint8_t*)&this->req->result,
|
|
|
|
this,
|
|
|
|
this->traceData);
|
|
|
|
} else {
|
|
|
|
panic("Unknown type!");
|
|
|
|
}
|
|
|
|
|
|
|
|
return this->fault;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
bool
|
|
|
|
OzoneDynInst<Impl>::srcInstReady(int regIdx)
|
|
|
|
{
|
Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
|
|
|
return srcInsts[regIdx]->isResultReady();
|
2006-04-23 00:45:01 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
OzoneDynInst<Impl>::addDependent(DynInstPtr &dependent_inst)
|
|
|
|
{
|
|
|
|
dependents.push_back(dependent_inst);
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
OzoneDynInst<Impl>::wakeDependents()
|
|
|
|
{
|
|
|
|
for (int i = 0; i < dependents.size(); ++i) {
|
|
|
|
dependents[i]->markSrcRegReady();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
OzoneDynInst<Impl>::wakeMemDependents()
|
|
|
|
{
|
|
|
|
for (int i = 0; i < memDependents.size(); ++i) {
|
|
|
|
memDependents[i]->markMemInstReady(this);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
OzoneDynInst<Impl>::markMemInstReady(OzoneDynInst<Impl> *inst)
|
|
|
|
{
|
|
|
|
ListIt mem_it = srcMemInsts.begin();
|
|
|
|
while ((*mem_it) != inst && mem_it != srcMemInsts.end()) {
|
|
|
|
mem_it++;
|
|
|
|
}
|
|
|
|
assert(mem_it != srcMemInsts.end());
|
|
|
|
|
|
|
|
srcMemInsts.erase(mem_it);
|
|
|
|
}
|
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
OzoneDynInst<Impl>::initInstPtrs()
|
|
|
|
{
|
|
|
|
for (int i = 0; i < MaxInstSrcRegs; ++i) {
|
|
|
|
srcInsts[i] = NULL;
|
|
|
|
}
|
|
|
|
iqItValid = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
bool
|
|
|
|
OzoneDynInst<Impl>::srcsReady()
|
|
|
|
{
|
|
|
|
for (int i = 0; i < this->numSrcRegs(); ++i) {
|
Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
|
|
|
if (!srcInsts[i]->isResultReady())
|
2006-04-23 00:45:01 +02:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
bool
|
|
|
|
OzoneDynInst<Impl>::eaSrcsReady()
|
|
|
|
{
|
|
|
|
for (int i = 1; i < this->numSrcRegs(); ++i) {
|
Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
|
|
|
if (!srcInsts[i]->isResultReady())
|
2006-04-23 00:45:01 +02:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
OzoneDynInst<Impl>::clearDependents()
|
|
|
|
{
|
|
|
|
dependents.clear();
|
|
|
|
for (int i = 0; i < this->numSrcRegs(); ++i) {
|
|
|
|
srcInsts[i] = NULL;
|
|
|
|
}
|
|
|
|
for (int i = 0; i < this->numDestRegs(); ++i) {
|
|
|
|
prevDestInst[i] = NULL;
|
|
|
|
}
|
|
|
|
}
|
Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
OzoneDynInst<Impl>::clearMemDependents()
|
|
|
|
{
|
|
|
|
memDependents.clear();
|
|
|
|
}
|
|
|
|
|
2006-04-23 00:45:01 +02:00
|
|
|
template <class Impl>
|
|
|
|
MiscReg
|
|
|
|
OzoneDynInst<Impl>::readMiscReg(int misc_reg)
|
|
|
|
{
|
|
|
|
return this->thread->readMiscReg(misc_reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
MiscReg
|
|
|
|
OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault)
|
|
|
|
{
|
|
|
|
return this->thread->readMiscRegWithEffect(misc_reg, fault);
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
Fault
|
|
|
|
OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
|
|
|
|
{
|
Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
|
|
|
this->setIntResult(val);
|
2006-04-23 00:45:01 +02:00
|
|
|
return this->thread->setMiscReg(misc_reg, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
Fault
|
|
|
|
OzoneDynInst<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
|
|
|
|
{
|
|
|
|
return this->thread->setMiscRegWithEffect(misc_reg, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
#if FULL_SYSTEM
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
Fault
|
|
|
|
OzoneDynInst<Impl>::hwrei()
|
|
|
|
{
|
|
|
|
if (!this->cpu->inPalMode(this->readPC()))
|
|
|
|
return new AlphaISA::UnimplementedOpcodeFault;
|
|
|
|
|
|
|
|
this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR));
|
|
|
|
|
Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-12 01:18:36 +02:00
|
|
|
this->cpu->hwrei();
|
2006-04-23 00:45:01 +02:00
|
|
|
|
|
|
|
// FIXME: XXX check for interrupts? XXX
|
|
|
|
return NoFault;
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
int
|
|
|
|
OzoneDynInst<Impl>::readIntrFlag()
|
|
|
|
{
|
|
|
|
return this->cpu->readIntrFlag();
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
OzoneDynInst<Impl>::setIntrFlag(int val)
|
|
|
|
{
|
|
|
|
this->cpu->setIntrFlag(val);
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
bool
|
|
|
|
OzoneDynInst<Impl>::inPalMode()
|
|
|
|
{
|
|
|
|
return this->cpu->inPalMode();
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
OzoneDynInst<Impl>::trap(Fault fault)
|
|
|
|
{
|
|
|
|
fault->invoke(this->thread->getXCProxy());
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class Impl>
|
|
|
|
bool
|
|
|
|
OzoneDynInst<Impl>::simPalCheck(int palFunc)
|
|
|
|
{
|
|
|
|
return this->cpu->simPalCheck(palFunc);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
template <class Impl>
|
|
|
|
void
|
|
|
|
OzoneDynInst<Impl>::syscall()
|
|
|
|
{
|
|
|
|
this->cpu->syscall();
|
|
|
|
}
|
|
|
|
#endif
|