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gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt

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stats: update and fix e273e86a873d
2016-05-31 17:55:47 +02:00
---------- Begin Simulation Statistics ----------
sim_seconds 0.361598 # Number of seconds simulated
sim_ticks 361597758500 # Number of ticks simulated
final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
stats: update references
2016-07-21 18:19:18 +02:00
host_inst_rate 1165746 # Simulator instruction rate (inst/s)
host_op_rate 1165794 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1728825291 # Simulator tick rate (ticks/s)
host_mem_usage 381188 # Number of bytes of host memory used
host_seconds 209.16 # Real time elapsed on the host
stats: update and fix e273e86a873d
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sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
stats: update and fix e273e86a873d
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system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s)
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
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system.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
stats: update and fix e273e86a873d
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system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.workload.num_syscalls 443 # Number of system calls
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateResidencyTicks::ON 361597758500 # Cumulative time (in ticks) in various power states
stats: update and fix e273e86a873d
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system.cpu.numCycles 723195517 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 243825150 # Number of instructions committed
system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
system.cpu.num_int_insts 194726494 # number of integer instructions
system.cpu.num_fp_insts 11630 # number of float instructions
system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written
system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
system.cpu.num_mem_refs 105711441 # number of memory refs
system.cpu.num_load_insts 82803521 # Number of load instructions
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 29302884 # Number of branches fetched
system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction
system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 244431613 # Class of executed instruction
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
stats: update and fix e273e86a873d
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system.cpu.dcache.tags.replacements 935475 # number of replacements
system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
stats: update and fix e273e86a873d
2016-05-31 17:55:47 +02:00
system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
system.cpu.dcache.writebacks::total 935266 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
stats: update and fix e273e86a873d
2016-05-31 17:55:47 +02:00
system.cpu.icache.tags.replacements 25 # number of replacements
system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
stats: update and fix e273e86a873d
2016-05-31 17:55:47 +02:00
system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits
system.cpu.icache.overall_hits::total 244420617 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
system.cpu.icache.overall_misses::total 882 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 25 # number of writebacks
system.cpu.icache.writebacks::total 25 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
stats: update and fix e273e86a873d
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
stats: update and fix e273e86a873d
2016-05-31 17:55:47 +02:00
system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits
system.cpu.l2cache.overall_hits::total 924850 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
stats: update and fix e273e86a873d
2016-05-31 17:55:47 +02:00
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
stats: update references
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
stats: update and fix e273e86a873d
2016-05-31 17:55:47 +02:00
system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
stats: update and fix e273e86a873d
2016-05-31 17:55:47 +02:00
system.membus.trans_dist::ReadResp 1036 # Transaction distribution
system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
stats: update references
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
stats: update and fix e273e86a873d
2016-05-31 17:55:47 +02:00
system.membus.snoop_fanout::samples 15603 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 15603 # Request fanout histogram
system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
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