2014-07-23 23:09:04 +02:00
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/*
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* Copyright (c) 2013-2014 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andrew Bardsley
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*/
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/*
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* These classes define an expression language over uint64_t with only
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* a few operators. This can be used to form expressions for the extra
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* delay required in variable execution time instructions.
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*
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* Expressions, in evaluation, will have access to the ThreadContext and
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* a StaticInst.
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*/
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#ifndef __CPU_TIMING_EXPR_HH__
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#define __CPU_TIMING_EXPR_HH__
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "enums/TimingExprOp.hh"
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#include "params/TimingExpr.hh"
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#include "params/TimingExprBin.hh"
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#include "params/TimingExprIf.hh"
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#include "params/TimingExprLet.hh"
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#include "params/TimingExprLiteral.hh"
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#include "params/TimingExprReadIntReg.hh"
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#include "params/TimingExprRef.hh"
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#include "params/TimingExprSrcReg.hh"
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#include "params/TimingExprUn.hh"
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#include "sim/sim_object.hh"
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/** These classes are just the C++ counterparts for those in Expr.py and
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* are, therefore, documented there */
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class TimingExprLet;
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/** Object to gather the visible context for evaluation */
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class TimingExprEvalContext
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{
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public:
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/** Special visible context */
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2014-09-27 15:08:36 +02:00
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const StaticInstPtr &inst;
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2014-07-23 23:09:04 +02:00
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ThreadContext *thread;
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/** Context visible as sub expressions. results will hold the results
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* of (lazily) evaluating let's expressions. resultAvailable elements
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* are true when a result has actually been evaluated */
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TimingExprLet *let;
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std::vector<uint64_t> results;
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std::vector<bool > resultAvailable;
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2014-09-27 15:08:36 +02:00
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TimingExprEvalContext(const StaticInstPtr &inst_,
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2014-07-23 23:09:04 +02:00
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ThreadContext *thread_, TimingExprLet *let_);
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};
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class TimingExpr : public SimObject
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{
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public:
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TimingExpr(const TimingExprParams *params) :
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SimObject(params)
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{ }
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virtual uint64_t eval(TimingExprEvalContext &context) = 0;
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};
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class TimingExprLiteral : public TimingExpr
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{
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public:
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uint64_t value;
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TimingExprLiteral(const TimingExprLiteralParams *params) :
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TimingExpr(params),
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value(params->value)
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{ }
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uint64_t eval(TimingExprEvalContext &context) { return value; }
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};
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class TimingExprSrcReg : public TimingExpr
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{
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public:
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unsigned int index;
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TimingExprSrcReg(const TimingExprSrcRegParams *params) :
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TimingExpr(params),
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index(params->index)
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{ }
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uint64_t eval(TimingExprEvalContext &context);
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};
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class TimingExprReadIntReg : public TimingExpr
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{
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public:
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TimingExpr *reg;
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TimingExprReadIntReg(const TimingExprReadIntRegParams *params) :
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TimingExpr(params),
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reg(params->reg)
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{ }
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uint64_t eval(TimingExprEvalContext &context);
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};
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class TimingExprLet : public TimingExpr
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{
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public:
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std::vector<TimingExpr *> defns;
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TimingExpr *expr;
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TimingExprLet(const TimingExprLetParams *params) :
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TimingExpr(params),
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defns(params->defns),
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expr(params->expr)
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{ }
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uint64_t eval(TimingExprEvalContext &context);
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};
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class TimingExprRef : public TimingExpr
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{
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public:
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unsigned int index;
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TimingExprRef(const TimingExprRefParams *params) :
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TimingExpr(params),
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index(params->index)
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{ }
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uint64_t eval(TimingExprEvalContext &context);
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};
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class TimingExprUn : public TimingExpr
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{
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public:
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Enums::TimingExprOp op;
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TimingExpr *arg;
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TimingExprUn(const TimingExprUnParams *params) :
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TimingExpr(params),
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op(params->op),
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arg(params->arg)
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{ }
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uint64_t eval(TimingExprEvalContext &context);
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};
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class TimingExprBin : public TimingExpr
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{
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public:
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Enums::TimingExprOp op;
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TimingExpr *left;
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TimingExpr *right;
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TimingExprBin(const TimingExprBinParams *params) :
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TimingExpr(params),
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op(params->op),
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left(params->left),
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right(params->right)
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{ }
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uint64_t eval(TimingExprEvalContext &context);
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};
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class TimingExprIf : public TimingExpr
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{
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public:
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TimingExpr *cond;
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TimingExpr *trueExpr;
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TimingExpr *falseExpr;
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TimingExprIf(const TimingExprIfParams *params) :
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TimingExpr(params),
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cond(params->cond),
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trueExpr(params->trueExpr),
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falseExpr(params->falseExpr)
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{ }
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uint64_t eval(TimingExprEvalContext &context);
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};
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#endif
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