2012-05-23 15:15:45 +02:00
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/*
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2015-08-07 10:59:23 +02:00
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* Copyright (c) 2012, 2015 ARM Limited
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2012-05-23 15:15:45 +02:00
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Nathan Binkert
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2012-08-22 17:40:01 +02:00
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* Andreas Hansson
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2015-08-07 10:59:23 +02:00
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* Andreas Sandberg
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2012-05-23 15:15:45 +02:00
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*/
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2015-08-07 10:59:23 +02:00
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#include "dev/dma_device.hh"
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#include <utility>
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2012-05-23 15:15:45 +02:00
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#include "base/chunk_generator.hh"
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#include "debug/DMA.hh"
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2012-08-15 16:38:08 +02:00
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#include "debug/Drain.hh"
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2012-05-23 15:15:45 +02:00
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#include "sim/system.hh"
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2012-08-22 17:39:59 +02:00
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DmaPort::DmaPort(MemObject *dev, System *s)
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2015-08-07 10:59:23 +02:00
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: MasterPort(dev->name() + ".dma", dev),
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device(dev), sys(s), masterId(s->getMasterId(dev->name())),
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sendEvent(this), pendingCount(0), inRetry(false)
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2012-05-23 15:15:45 +02:00
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{ }
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2012-08-22 17:40:01 +02:00
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void
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DmaPort::handleResp(PacketPtr pkt, Tick delay)
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2012-05-23 15:15:45 +02:00
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{
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2012-08-22 17:40:01 +02:00
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// should always see a response with a sender state
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assert(pkt->isResponse());
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// get the DMA sender state
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DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState);
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assert(state);
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DPRINTF(DMA, "Received response %s for addr: %#x size: %d nb: %d," \
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" tot: %d sched %d\n",
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pkt->cmdString(), pkt->getAddr(), pkt->req->getSize(),
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state->numBytes, state->totBytes,
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state->completionEvent ?
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state->completionEvent->scheduled() : 0);
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assert(pendingCount != 0);
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pendingCount--;
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// update the number of bytes received based on the request rather
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// than the packet as the latter could be rounded up to line sizes
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state->numBytes += pkt->req->getSize();
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assert(state->totBytes >= state->numBytes);
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// if we have reached the total number of bytes for this DMA
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// request, then signal the completion and delete the sate
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if (state->totBytes == state->numBytes) {
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if (state->completionEvent) {
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delay += state->delay;
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2013-01-07 22:56:39 +01:00
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device->schedule(state->completionEvent, curTick() + delay);
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2012-05-23 15:15:45 +02:00
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}
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2012-08-22 17:40:01 +02:00
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delete state;
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}
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2012-05-23 15:15:45 +02:00
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2012-08-22 17:40:01 +02:00
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// delete the request that we created and also the packet
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delete pkt->req;
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delete pkt;
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// we might be drained at this point, if so signal the drain event
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2015-07-07 10:51:05 +02:00
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if (pendingCount == 0)
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signalDrainDone();
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2012-08-22 17:40:01 +02:00
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}
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bool
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DmaPort::recvTimingResp(PacketPtr pkt)
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{
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2015-12-31 15:32:58 +01:00
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// We shouldn't ever get a cacheable block in Modified state
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2015-05-05 09:22:29 +02:00
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assert(pkt->req->isUncacheable() ||
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2015-12-31 15:32:58 +01:00
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!(pkt->cacheResponding() && !pkt->hasSharers()));
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2012-08-22 17:40:01 +02:00
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handleResp(pkt);
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2012-05-23 15:15:45 +02:00
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return true;
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}
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DmaDevice::DmaDevice(const Params *p)
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2012-08-22 17:39:59 +02:00
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: PioDevice(p), dmaPort(this, sys)
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2012-05-23 15:15:45 +02:00
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{ }
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void
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DmaDevice::init()
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{
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if (!dmaPort.isConnected())
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panic("DMA port of %s not connected to anything!", name());
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PioDevice::init();
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}
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2015-07-07 10:51:05 +02:00
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DrainState
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DmaPort::drain()
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2012-05-23 15:15:45 +02:00
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{
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2015-07-07 10:51:05 +02:00
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if (pendingCount == 0) {
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return DrainState::Drained;
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} else {
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DPRINTF(Drain, "DmaPort not drained\n");
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return DrainState::Draining;
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}
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2012-05-23 15:15:45 +02:00
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}
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void
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2015-03-02 10:00:35 +01:00
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DmaPort::recvReqRetry()
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2012-05-23 15:15:45 +02:00
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{
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assert(transmitList.size());
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2012-10-23 10:49:33 +02:00
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trySendTimingReq();
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2012-05-23 15:15:45 +02:00
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}
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2014-12-23 15:31:18 +01:00
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RequestPtr
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2012-05-23 15:15:45 +02:00
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DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
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uint8_t *data, Tick delay, Request::Flags flag)
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{
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2012-08-22 17:40:01 +02:00
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// one DMA request sender state for every action, that is then
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// split into many requests and packets based on the block size,
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// i.e. cache line size
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2012-05-23 15:15:45 +02:00
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DmaReqState *reqState = new DmaReqState(event, size, delay);
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2014-12-23 15:31:18 +01:00
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// (functionality added for Table Walker statistics)
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// We're only interested in this when there will only be one request.
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// For simplicity, we return the last request, which would also be
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// the only request in that case.
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RequestPtr req = NULL;
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2012-05-23 15:15:45 +02:00
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DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
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2012-08-22 17:40:01 +02:00
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event ? event->scheduled() : -1);
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2013-07-18 14:31:16 +02:00
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for (ChunkGenerator gen(addr, size, sys->cacheLineSize());
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2012-05-23 15:15:45 +02:00
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!gen.done(); gen.next()) {
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2014-12-23 15:31:18 +01:00
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req = new Request(gen.addr(), gen.size(), flag, masterId);
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2014-01-24 22:29:30 +01:00
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req->taskId(ContextSwitchTaskId::DMA);
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2012-08-22 17:40:01 +02:00
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PacketPtr pkt = new Packet(req, cmd);
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2012-05-23 15:15:45 +02:00
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2012-08-22 17:40:01 +02:00
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// Increment the data pointer on a write
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if (data)
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pkt->dataStatic(data + gen.complete());
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2012-05-23 15:15:45 +02:00
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2012-08-22 17:40:01 +02:00
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pkt->senderState = reqState;
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2012-05-23 15:15:45 +02:00
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2012-08-22 17:40:01 +02:00
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DPRINTF(DMA, "--Queuing DMA for addr: %#x size: %d\n", gen.addr(),
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gen.size());
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queueDma(pkt);
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2012-05-23 15:15:45 +02:00
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}
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2012-10-23 10:49:33 +02:00
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// in zero time also initiate the sending of the packets we have
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// just created, for atomic this involves actually completing all
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// the requests
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sendDma();
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2014-12-23 15:31:18 +01:00
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return req;
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2012-05-23 15:15:45 +02:00
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}
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void
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2012-08-22 17:40:01 +02:00
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DmaPort::queueDma(PacketPtr pkt)
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2012-05-23 15:15:45 +02:00
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{
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2012-08-22 17:40:01 +02:00
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transmitList.push_back(pkt);
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// remember that we have another packet pending, this will only be
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// decremented once a response comes back
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pendingCount++;
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2012-10-23 10:49:33 +02:00
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}
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2012-05-23 15:15:45 +02:00
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2012-10-23 10:49:33 +02:00
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void
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DmaPort::trySendTimingReq()
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{
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// send the first packet on the transmit list and schedule the
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// following send if it is successful
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PacketPtr pkt = transmitList.front();
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DPRINTF(DMA, "Trying to send %s addr %#x\n", pkt->cmdString(),
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pkt->getAddr());
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inRetry = !sendTimingReq(pkt);
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if (!inRetry) {
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transmitList.pop_front();
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DPRINTF(DMA, "-- Done\n");
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// if there is more to do, then do so
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if (!transmitList.empty())
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// this should ultimately wait for as many cycles as the
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// device needs to send the packet, but currently the port
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// does not have any known width so simply wait a single
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// cycle
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device->schedule(sendEvent, device->clockEdge(Cycles(1)));
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} else {
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DPRINTF(DMA, "-- Failed, waiting for retry\n");
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}
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DPRINTF(DMA, "TransmitList: %d, inRetry: %d\n",
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transmitList.size(), inRetry);
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2012-05-23 15:15:45 +02:00
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}
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void
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DmaPort::sendDma()
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{
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2012-08-22 17:40:01 +02:00
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// some kind of selcetion between access methods
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2012-05-23 15:15:45 +02:00
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// more work is going to have to be done to make
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// switching actually work
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assert(transmitList.size());
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2013-02-15 23:40:09 +01:00
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if (sys->isTimingMode()) {
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2012-10-23 10:49:33 +02:00
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// if we are either waiting for a retry or are still waiting
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// after sending the last packet, then do not proceed
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if (inRetry || sendEvent.scheduled()) {
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DPRINTF(DMA, "Can't send immediately, waiting to send\n");
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2012-05-23 15:15:45 +02:00
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return;
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}
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2012-10-23 10:49:33 +02:00
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trySendTimingReq();
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2013-02-15 23:40:09 +01:00
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} else if (sys->isAtomicMode()) {
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2012-10-23 10:49:33 +02:00
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// send everything there is to send in zero time
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while (!transmitList.empty()) {
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PacketPtr pkt = transmitList.front();
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transmitList.pop_front();
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2012-05-23 15:15:45 +02:00
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2012-10-23 10:49:33 +02:00
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DPRINTF(DMA, "Sending DMA for addr: %#x size: %d\n",
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pkt->req->getPaddr(), pkt->req->getSize());
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Tick lat = sendAtomic(pkt);
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2012-05-23 15:15:45 +02:00
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2012-10-23 10:49:33 +02:00
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handleResp(pkt, lat);
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}
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2012-08-22 17:40:01 +02:00
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} else
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panic("Unknown memory mode.");
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2012-05-23 15:15:45 +02:00
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}
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2012-10-15 14:12:35 +02:00
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BaseMasterPort &
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DmaDevice::getMasterPort(const std::string &if_name, PortID idx)
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2012-05-23 15:15:45 +02:00
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{
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if (if_name == "dma") {
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return dmaPort;
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}
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return PioDevice::getMasterPort(if_name, idx);
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}
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2015-08-07 10:59:23 +02:00
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DmaReadFifo::DmaReadFifo(DmaPort &_port, size_t size,
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unsigned max_req_size,
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unsigned max_pending,
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Request::Flags flags)
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: maxReqSize(max_req_size), fifoSize(size),
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reqFlags(flags), port(_port),
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buffer(size),
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nextAddr(0), endAddr(0)
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{
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freeRequests.resize(max_pending);
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for (auto &e : freeRequests)
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e.reset(new DmaDoneEvent(this, max_req_size));
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}
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DmaReadFifo::~DmaReadFifo()
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{
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for (auto &p : pendingRequests) {
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DmaDoneEvent *e(p.release());
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if (e->done()) {
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delete e;
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} else {
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// We can't kill in-flight DMAs, so we'll just transfer
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// ownership to the event queue so that they get freed
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// when they are done.
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e->kill();
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}
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}
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}
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void
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DmaReadFifo::serialize(CheckpointOut &cp) const
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{
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assert(pendingRequests.empty());
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SERIALIZE_CONTAINER(buffer);
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SERIALIZE_SCALAR(endAddr);
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SERIALIZE_SCALAR(nextAddr);
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}
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void
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DmaReadFifo::unserialize(CheckpointIn &cp)
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{
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UNSERIALIZE_CONTAINER(buffer);
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UNSERIALIZE_SCALAR(endAddr);
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UNSERIALIZE_SCALAR(nextAddr);
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}
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bool
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DmaReadFifo::tryGet(uint8_t *dst, size_t len)
|
|
|
|
{
|
|
|
|
if (buffer.size() >= len) {
|
|
|
|
buffer.read(dst, len);
|
|
|
|
resumeFill();
|
|
|
|
return true;
|
|
|
|
} else {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DmaReadFifo::get(uint8_t *dst, size_t len)
|
|
|
|
{
|
|
|
|
const bool success(tryGet(dst, len));
|
|
|
|
panic_if(!success, "Buffer underrun in DmaReadFifo::get()\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DmaReadFifo::startFill(Addr start, size_t size)
|
|
|
|
{
|
|
|
|
assert(atEndOfBlock());
|
|
|
|
|
|
|
|
nextAddr = start;
|
|
|
|
endAddr = start + size;
|
|
|
|
resumeFill();
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DmaReadFifo::stopFill()
|
|
|
|
{
|
|
|
|
// Prevent new DMA requests by setting the next address to the end
|
|
|
|
// address. Pending requests will still complete.
|
|
|
|
nextAddr = endAddr;
|
|
|
|
|
|
|
|
// Flag in-flight accesses as canceled. This prevents their data
|
|
|
|
// from being written to the FIFO.
|
|
|
|
for (auto &p : pendingRequests)
|
|
|
|
p->cancel();
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DmaReadFifo::resumeFill()
|
|
|
|
{
|
|
|
|
// Don't try to fetch more data if we are draining. This ensures
|
|
|
|
// that the DMA engine settles down before we checkpoint it.
|
|
|
|
if (drainState() == DrainState::Draining)
|
|
|
|
return;
|
|
|
|
|
|
|
|
const bool old_eob(atEndOfBlock());
|
|
|
|
size_t size_pending(0);
|
|
|
|
for (auto &e : pendingRequests)
|
|
|
|
size_pending += e->requestSize();
|
|
|
|
|
|
|
|
while (!freeRequests.empty() && !atEndOfBlock()) {
|
|
|
|
const size_t req_size(std::min(maxReqSize, endAddr - nextAddr));
|
|
|
|
if (buffer.size() + size_pending + req_size > fifoSize)
|
|
|
|
break;
|
|
|
|
|
|
|
|
DmaDoneEventUPtr event(std::move(freeRequests.front()));
|
|
|
|
freeRequests.pop_front();
|
|
|
|
assert(event);
|
|
|
|
|
|
|
|
event->reset(req_size);
|
|
|
|
port.dmaAction(MemCmd::ReadReq, nextAddr, req_size, event.get(),
|
|
|
|
event->data(), 0, reqFlags);
|
|
|
|
nextAddr += req_size;
|
|
|
|
size_pending += req_size;
|
|
|
|
|
|
|
|
pendingRequests.emplace_back(std::move(event));
|
|
|
|
}
|
|
|
|
|
|
|
|
// EOB can be set before a call to dmaDone() if in-flight accesses
|
|
|
|
// have been canceled.
|
|
|
|
if (!old_eob && atEndOfBlock())
|
|
|
|
onEndOfBlock();
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DmaReadFifo::dmaDone()
|
|
|
|
{
|
|
|
|
const bool old_active(isActive());
|
|
|
|
|
|
|
|
handlePending();
|
|
|
|
resumeFill();
|
|
|
|
|
|
|
|
if (!old_active && isActive())
|
|
|
|
onIdle();
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DmaReadFifo::handlePending()
|
|
|
|
{
|
|
|
|
while (!pendingRequests.empty() && pendingRequests.front()->done()) {
|
|
|
|
// Get the first finished pending request
|
|
|
|
DmaDoneEventUPtr event(std::move(pendingRequests.front()));
|
|
|
|
pendingRequests.pop_front();
|
|
|
|
|
|
|
|
if (!event->canceled())
|
|
|
|
buffer.write(event->data(), event->requestSize());
|
|
|
|
|
|
|
|
// Move the event to the list of free requests
|
|
|
|
freeRequests.emplace_back(std::move(event));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pendingRequests.empty())
|
|
|
|
signalDrainDone();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DrainState
|
|
|
|
DmaReadFifo::drain()
|
|
|
|
{
|
|
|
|
return pendingRequests.empty() ? DrainState::Drained : DrainState::Draining;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
DmaReadFifo::DmaDoneEvent::DmaDoneEvent(DmaReadFifo *_parent,
|
|
|
|
size_t max_size)
|
|
|
|
: parent(_parent), _done(false), _canceled(false), _data(max_size, 0)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DmaReadFifo::DmaDoneEvent::kill()
|
|
|
|
{
|
|
|
|
parent = nullptr;
|
|
|
|
setFlags(AutoDelete);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DmaReadFifo::DmaDoneEvent::cancel()
|
|
|
|
{
|
|
|
|
_canceled = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DmaReadFifo::DmaDoneEvent::reset(size_t size)
|
|
|
|
{
|
|
|
|
assert(size <= _data.size());
|
|
|
|
_done = false;
|
|
|
|
_canceled = false;
|
|
|
|
_requestSize = size;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
DmaReadFifo::DmaDoneEvent::process()
|
|
|
|
{
|
|
|
|
if (!parent)
|
|
|
|
return;
|
|
|
|
|
|
|
|
assert(!_done);
|
|
|
|
_done = true;
|
|
|
|
parent->dmaDone();
|
|
|
|
}
|