2015-04-23 19:37:49 +02:00
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/*
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* Copyright (c) 2013-2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Rene de Jong
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*/
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#ifndef __DEV_ARM_FLASH_DEVICE_HH__
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#define __DEV_ARM_FLASH_DEVICE_HH__
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#include <deque>
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#include "base/statistics.hh"
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#include "debug/FlashDevice.hh"
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#include "dev/arm/abstract_nvm.hh"
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#include "enums/DataDistribution.hh"
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#include "params/FlashDevice.hh"
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#include "sim/serialize.hh"
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/**
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* Flash Device model
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* The Flash Device model is a timing model for a NAND flash device.
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* It doesn't tranfer any data
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*/
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class FlashDevice : public AbstractNVM
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{
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public:
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/** Initialize functions*/
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FlashDevice(const FlashDeviceParams*);
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~FlashDevice();
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/** Checkpoint functions*/
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2015-07-07 10:51:05 +02:00
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DrainState drain() M5_ATTR_OVERRIDE;
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2015-04-23 19:37:49 +02:00
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void checkDrain();
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2015-07-07 10:51:03 +02:00
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void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
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void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
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2015-04-23 19:37:49 +02:00
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private:
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/** Defines the possible actions to the flash*/
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enum Actions {
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ActionRead,
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ActionWrite,
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ActionErase,
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/**
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* A copy involves taking all the used pages from a block and store
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* it in another
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*/
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ActionCopy
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};
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/** Every logical address maps to a physical block and a physical page*/
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struct PageMapEntry {
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uint32_t page;
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uint32_t block;
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};
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struct CallBackEntry {
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Tick time;
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Callback *function;
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};
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struct FlashDeviceStats {
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/** Amount of GC activations*/
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Stats::Scalar totalGCActivations;
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/** Histogram of address accesses*/
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Stats::Histogram writeAccess;
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Stats::Histogram readAccess;
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Stats::Histogram fileSystemAccess;
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/** Histogram of access latencies*/
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Stats::Histogram writeLatency;
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Stats::Histogram readLatency;
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};
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/** Device access functions Inherrited from AbstractNVM*/
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virtual void initializeMemory(uint64_t disk_size, uint32_t sector_size)
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{
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initializeFlash(disk_size, sector_size);
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}
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virtual void readMemory(uint64_t address, uint32_t amount,
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Callback *event)
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{
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accessDevice(address, amount, event, ActionRead);
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}
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virtual void writeMemory(uint64_t address, uint32_t amount,
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Callback *event)
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{
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accessDevice(address, amount, event, ActionWrite);
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}
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/**Initialization function; called when all disk specifics are known*/
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void initializeFlash(uint64_t disk_size, uint32_t sector_size);
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/**Flash action function*/
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void accessDevice(uint64_t address, uint32_t amount, Callback *event,
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Actions action);
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/** Event rescheduler*/
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void actionComplete();
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/** FTL functionality */
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Tick remap(uint64_t logic_page_addr);
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/** Access time calculator*/
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Tick accessTimes(uint64_t address, Actions accesstype);
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/** Function to indicate that a page is known*/
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void clearUnknownPages(uint32_t index);
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/** Function to test if a page is known*/
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bool getUnknownPages(uint32_t index);
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/**Stats register function*/
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void regStats();
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/** Disk sizes in bytes */
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uint64_t diskSize;
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const uint32_t blockSize;
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const uint32_t pageSize;
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/** Garbage collection algorithm emulator */
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const uint32_t GCActivePercentage;
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/** Access latencies */
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const Tick readLatency;
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const Tick writeLatency;
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const Tick eraseLatency;
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/** Flash organization */
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const Enums::DataDistribution dataDistribution;
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const uint32_t numPlanes;
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/** RequestHandler stats */
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struct FlashDeviceStats stats;
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/** Disk dimensions in pages and blocks */
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uint32_t pagesPerBlock;
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uint32_t pagesPerDisk;
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uint32_t blocksPerDisk;
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uint32_t planeMask;
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/**
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* when the disk is first started we are unsure of the number of
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* used pages, this variable will help determining what we do know.
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*/
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std::vector<uint32_t> unknownPages;
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/** address to logic place has a block and a page field*/
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std::vector<struct PageMapEntry> locationTable;
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/** number of valid entries per block*/
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std::vector<uint32_t> blockValidEntries;
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/** number of empty entries*/
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std::vector<uint32_t> blockEmptyEntries;
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/**This vector of queues keeps track of all the callbacks per plane*/
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std::vector<std::deque<struct CallBackEntry> > planeEventQueue;
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/** Completion event */
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EventWrapper<FlashDevice, &FlashDevice::actionComplete> planeEvent;
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};
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#endif //__DEV_ARM_FLASH_DEVICE_HH__
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