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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt

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tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
sim_seconds 1.841686 # Number of seconds simulated
sim_ticks 1841685645500 # Number of ticks simulated
final_tick 1841685645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
host_inst_rate 340884 # Simulator instruction rate (inst/s)
host_op_rate 340884 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 9045969324 # Simulator tick rate (ticks/s)
host_mem_usage 315876 # Number of bytes of host memory used
host_seconds 203.59 # Real time elapsed on the host
sim_insts 69401254 # Number of instructions simulated
sim_ops 69401254 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 474368 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 19389440 # Number of bytes read from this memory
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.bytes_read::cpu1.inst 150272 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 2812736 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 293952 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 2665600 # Number of bytes read from this memory
system.physmem.bytes_read::total 28438656 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 474368 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 150272 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 293952 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 918592 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7476160 # Number of bytes written to this memory
system.physmem.bytes_written::total 7476160 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 7412 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 302960 # Number of read requests responded to by this memory
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.num_reads::cpu1.inst 2348 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 43949 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 4593 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 41650 # Number of read requests responded to by this memory
system.physmem.num_reads::total 444354 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 116815 # Number of write requests responded to by this memory
system.physmem.num_writes::total 116815 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 257573 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 10528094 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1440142 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 81595 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1527262 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 159610 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 1447370 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15441645 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 257573 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 81595 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 159610 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 498778 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4059412 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4059412 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4059412 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 257573 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 10528094 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1440142 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 81595 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1527262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 159610 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1447370 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19501057 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 109303 # Total number of read requests seen
system.physmem.writeReqs 45531 # Total number of write requests seen
system.physmem.cpureqs 156037 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 6995392 # Total number of bytes read from memory
system.physmem.bytesWritten 2913984 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 6995392 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 2913984 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.neitherReadNorWrite 41 # Reqs where no action is needed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.perBankRdReqs::0 6941 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 6714 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 6576 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 6492 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 6845 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 6834 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 6769 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 6799 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 7016 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 6828 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 7161 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 6927 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 6799 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 6925 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 6890 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 6781 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 2987 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 2793 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 2679 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 2608 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 2843 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 2755 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 2723 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 2826 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 3041 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 2937 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 3162 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 2868 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 2817 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 2876 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 2850 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 2766 # Track writes on a per bank basis
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.numWrRetry 1002 # Number of times wr buffer was full causing retry
system.physmem.totGap 1840673558000 # Total gap between requests
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.readPktSize::6 109303 # Categorize read packet sizes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.writePktSize::6 46533 # categorize write packet sizes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 41 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.rdQLenPdf::0 80133 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 9534 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 5401 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1969 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1272 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1200 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1099 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1096 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1079 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1052 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 614 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 596 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 576 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 554 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 569 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 582 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 666 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 614 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 379 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.wrQLenPdf::0 1276 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1626 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1648 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1852 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1983 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1976 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1975 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1979 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1979 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1975 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1973 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1971 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1969 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1969 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 1964 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 1962 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 1960 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 1960 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 1957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 1957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 757 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 571 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 375 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 351 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.totQLat 2420382927 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 4417685427 # Sum of mem lat for all requests
system.physmem.totBusLat 546485000 # Total cycles spent in databus access
system.physmem.totBankLat 1450817500 # Total cycles spent in bank access
system.physmem.avgQLat 22145.01 # Average queueing delay per request
system.physmem.avgBankLat 13274.08 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 40419.09 # Average memory access latency
system.physmem.avgRdBW 3.80 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.80 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 1.58 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.avgRdQLen 0.00 # Average read queue length over time
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.physmem.avgWrQLen 0.16 # Average write queue length over time
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.readRowHits 99113 # Number of row buffer hits during reads
system.physmem.writeRowHits 34331 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.68 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.40 # Row buffer hit rate for writes
system.physmem.avgGap 11888044.99 # Average gap between requests
system.l2c.replacements 337419 # number of replacements
system.l2c.tagsinuse 65421.239766 # Cycle average of tags in use
system.l2c.total_refs 2475143 # Total number of references to valid blocks.
system.l2c.sampled_refs 402581 # Sample count of references to valid blocks.
system.l2c.avg_refs 6.148186 # Average number of references to valid blocks.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.occ_blocks::writebacks 54789.025804 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 2312.416873 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 2671.189078 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 589.820867 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 668.130775 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst 2247.184130 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.data 2143.472239 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.836014 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.035285 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.040759 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.009000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.010195 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.inst 0.034289 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2.data 0.032707 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.998249 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 513915 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 491176 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 126581 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 82893 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 298491 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 243008 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1756064 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 836144 # number of Writeback hits
system.l2c.Writeback_hits::total 836144 # number of Writeback hits
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.l2c.UpgradeReq_hits::cpu2.data 4 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 8 # number of UpgradeReq hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadExReq_hits::cpu0.data 92052 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 27044 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 67842 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 186938 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 513915 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 583228 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 126581 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 109937 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 298491 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 310850 # number of demand (read+write) hits
system.l2c.demand_hits::total 1943002 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 513915 # number of overall hits
system.l2c.overall_hits::cpu0.data 583228 # number of overall hits
system.l2c.overall_hits::cpu1.inst 126581 # number of overall hits
system.l2c.overall_hits::cpu1.data 109937 # number of overall hits
system.l2c.overall_hits::cpu2.inst 298491 # number of overall hits
system.l2c.overall_hits::cpu2.data 310850 # number of overall hits
system.l2c.overall_hits::total 1943002 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 7412 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 226081 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 2348 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 22980 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 4593 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 24148 # number of ReadReq misses
system.l2c.ReadReq_misses::total 287562 # number of ReadReq misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.UpgradeReq_misses::cpu2.data 11 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 19 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 77155 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 21018 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 17603 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 115776 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 7412 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 303236 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2348 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 43998 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 4593 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 41751 # number of demand (read+write) misses
system.l2c.demand_misses::total 403338 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 7412 # number of overall misses
system.l2c.overall_misses::cpu0.data 303236 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2348 # number of overall misses
system.l2c.overall_misses::cpu1.data 43998 # number of overall misses
system.l2c.overall_misses::cpu2.inst 4593 # number of overall misses
system.l2c.overall_misses::cpu2.data 41751 # number of overall misses
system.l2c.overall_misses::total 403338 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst 154067000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 1052058500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 311891000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 1117922000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2635938500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 295000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 295000 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 978615000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 1291616000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 2270231000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst 154067000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 2030673500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 311891000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 2409538000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 4906169500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst 154067000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 2030673500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 311891000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 2409538000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 4906169500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 521327 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 717257 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 128929 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 105873 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 303084 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 267156 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2043626 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 836144 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 836144 # number of Writeback accesses(hits+misses)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 169207 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 48062 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 85445 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 302714 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 521327 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 886464 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 128929 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 153935 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 303084 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 352601 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2346340 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 521327 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 886464 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 128929 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 153935 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 303084 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 352601 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2346340 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014218 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.315202 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.018212 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.217053 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.015154 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.090389 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.140712 # miss rate for ReadReq accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.733333 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.703704 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.455980 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.437310 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.206016 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.382460 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014218 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.342074 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.018212 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.285822 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.015154 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.118409 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.171901 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014218 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.342074 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.018212 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.285822 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.015154 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.118409 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.171901 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 65616.269165 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 45781.483899 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 67905.726105 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 46294.599967 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 9166.504962 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 26818.181818 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 15526.315789 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46560.805024 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73374.765665 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 19608.822208 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 65616.269165 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 46153.768353 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 67905.726105 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 57712.102704 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 12163.915872 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 65616.269165 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 46153.768353 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 67905.726105 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 57712.102704 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 12163.915872 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.writebacks::writebacks 75303 # number of writebacks
system.l2c.writebacks::total 75303 # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu1.inst 2348 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 22980 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst 4593 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 24148 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 54069 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 11 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 21018 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 17603 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 38621 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 2348 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 43998 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 4593 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 41751 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 92690 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 2348 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 43998 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 4593 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 41751 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 92690 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 124527350 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 769462495 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 254593394 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 825079853 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1973663092 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 271507 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 271507 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 718879972 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1076725373 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1795605345 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 124527350 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1488342467 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 254593394 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 1901805226 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 3769268437 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 124527350 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1488342467 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 254593394 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 1901805226 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 3769268437 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269404000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320096500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 589500500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 337106000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 394521000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 731627000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 606510000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 714617500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 1321127500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018212 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.217053 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015154 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090389 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.026457 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.733333 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.407407 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.437310 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.206016 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.127582 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018212 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.285822 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015154 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.118409 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.039504 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018212 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.285822 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015154 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.118409 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.039504 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 33484.007615 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 55430.741128 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 34167.626843 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 36502.674213 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 24682.454545 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 24682.454545 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34203.062708 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61167.151792 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 46492.979079 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33827.502773 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 55430.741128 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 45551.129937 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40665.319204 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33827.502773 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 55430.741128 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 45551.129937 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40665.319204 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 41685 # number of replacements
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.iocache.tagsinuse 1.255467 # Cycle average of tags in use
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.iocache.warmup_cycle 1693876367000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 1.255467 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.078467 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.078467 # Average percentage of cache occupancy
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.iocache.ReadReq_miss_latency::tsunami.ide 10497998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 10497998 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 4320435904 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 4320435904 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 4330933902 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4330933902 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 4330933902 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4330933902 # number of overall miss cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 60682.069364 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 60682.069364 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103976.605314 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 103976.605314 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 103797.097711 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 103797.097711 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 103797.097711 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 103797.097711 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 116360 # number of cycles access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.iocache.blocked::no_mshrs 11123 # number of cycles access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 10.461207 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.iocache.WriteReq_mshr_misses::tsunami.ide 16768 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 16768 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 16837 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 16837 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 16837 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6909249 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 6909249 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3447972406 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 3447972406 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 3454881655 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 3454881655 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 3454881655 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 3454881655 # number of overall MSHR miss cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 0.403543 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.403523 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 100134.043478 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 100134.043478 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205628.125358 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 205628.125358 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205195.798242 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 205195.798242 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205195.798242 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 205195.798242 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dtb.read_hits 4870224 # DTB read hits
system.cpu0.dtb.read_misses 6004 # DTB read misses
system.cpu0.dtb.read_acv 119 # DTB read access violations
system.cpu0.dtb.read_accesses 427226 # DTB read accesses
system.cpu0.dtb.write_hits 3495920 # DTB write hits
system.cpu0.dtb.write_misses 662 # DTB write misses
system.cpu0.dtb.write_acv 82 # DTB write access violations
system.cpu0.dtb.write_accesses 162893 # DTB write accesses
system.cpu0.dtb.data_hits 8366144 # DTB hits
system.cpu0.dtb.data_misses 6666 # DTB misses
system.cpu0.dtb.data_acv 201 # DTB access violations
system.cpu0.dtb.data_accesses 590119 # DTB accesses
system.cpu0.itb.fetch_hits 2742252 # ITB hits
system.cpu0.itb.fetch_misses 2999 # ITB misses
system.cpu0.itb.fetch_acv 100 # ITB acv
system.cpu0.itb.fetch_accesses 2745251 # ITB accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.numCycles 928524557 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.committedInsts 32346409 # Number of instructions committed
system.cpu0.committedOps 32346409 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 30227601 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 167714 # Number of float alu accesses
system.cpu0.num_func_calls 807221 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4255838 # number of instructions that are conditional controls
system.cpu0.num_int_insts 30227601 # number of integer instructions
system.cpu0.num_fp_insts 167714 # number of float instructions
system.cpu0.num_int_register_reads 42120333 # number of times the integer registers were read
system.cpu0.num_int_register_writes 22107858 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 86620 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 88185 # number of times the floating registers were written
system.cpu0.num_mem_refs 8395831 # number of memory refs
system.cpu0.num_load_insts 4891260 # Number of load instructions
system.cpu0.num_store_insts 3504571 # Number of store instructions
system.cpu0.num_idle_cycles 213109834303.356140 # Number of idle cycles
system.cpu0.num_busy_cycles -212181309746.356140 # Number of busy cycles
system.cpu0.not_idle_fraction -228.514484 # Percentage of non-idle cycles
system.cpu0.idle_fraction 229.514484 # Percentage of idle cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 211363 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 74796 40.97% 40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.ipl_count::31 105684 57.89% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 182561 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 73429 49.30% 49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.ipl_good::31 73429 49.30% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 148939 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1818585880000 98.75% 98.75% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 39023000 0.00% 98.75% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 363355500 0.02% 98.77% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 22696630500 1.23% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1841684889000 # number of cycles we spent at this ipl
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.ipl_used::31 0.694798 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.815831 # fraction of swpipl calls that actually changed the ipl
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 326 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.callpal::swpipl 175304 91.20% 93.41% # number of callpals executed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.callpal::total 192218 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu0.kern.mode_good::kernel 1908
system.cpu0.kern.mode_good::user 1738
system.cpu0.kern.mode_good::idle 170
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.kern.mode_ticks::kernel 29741942000 1.61% 1.61% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 2557109000 0.14% 1.75% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 1809385834500 98.25% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 4178 # number of times the context was actually changed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.icache.replacements 952687 # number of replacements
system.cpu0.icache.tagsinuse 511.197182 # Cycle average of tags in use
system.cpu0.icache.total_refs 41854963 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 953198 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 43.910041 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 10248069000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 255.807414 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst 79.618511 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu2.inst 175.771256 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.499624 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst 0.155505 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu2.inst 0.343303 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.998432 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 31831928 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 7734859 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2288176 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 41854963 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 31831928 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 7734859 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 2288176 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 41854963 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 31831928 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 7734859 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 2288176 # number of overall hits
system.cpu0.icache.overall_hits::total 41854963 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 521348 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 128929 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 320069 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 970346 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 521348 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 128929 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 320069 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 970346 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 521348 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 128929 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 320069 # number of overall misses
system.cpu0.icache.overall_misses::total 970346 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1813964500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4473822486 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6287786986 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 1813964500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 4473822486 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6287786986 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 1813964500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 4473822486 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6287786986 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 32353276 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 7863788 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 2608245 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 42825309 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 32353276 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 7863788 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 2608245 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 42825309 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 32353276 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 7863788 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 2608245 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 42825309 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016114 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016395 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122714 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.022658 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016114 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016395 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122714 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.022658 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016114 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016395 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122714 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.022658 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14069.483980 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.681331 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 6479.943222 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14069.483980 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13977.681331 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 6479.943222 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14069.483980 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13977.681331 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 6479.943222 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 5140 # number of cycles access was blocked
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.icache.blocked::no_mshrs 170 # number of cycles access was blocked
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.235294 # average number of cycles each access was blocked
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16973 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 16973 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 16973 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 16973 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 16973 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 16973 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128929 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 303096 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 432025 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 128929 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 303096 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 432025 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 128929 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 303096 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 432025 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1556106500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3684192488 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 5240298988 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1556106500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3684192488 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 5240298988 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1556106500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3684192488 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 5240298988 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016395 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116207 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010088 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016395 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116207 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.010088 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016395 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116207 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.010088 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12155.199963 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12129.619786 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12155.199963 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12129.619786 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12155.199963 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12129.619786 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.replacements 1392453 # number of replacements
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.tagsinuse 511.997817 # Cycle average of tags in use
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.total_refs 13322506 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 1392965 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 9.564135 # Average number of references to valid blocks.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.occ_blocks::cpu0.data 248.356870 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data 87.947367 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu2.data 175.693580 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.485072 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data 0.171772 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu2.data 0.343152 # Average percentage of cache occupancy
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.ReadReq_hits::cpu0.data 4047371 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 1097591 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 2422188 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 7567150 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3200230 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 858461 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 1312963 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5371654 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116449 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19275 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 48623 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 184347 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125392 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21336 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 52561 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 199289 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 7247601 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 1956052 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 3735151 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 12938804 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 7247601 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 1956052 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 3735151 # number of overall hits
system.cpu0.dcache.overall_hits::total 12938804 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 707756 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 103680 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 547661 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1359097 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 169218 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 48063 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 563002 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 780283 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9501 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2193 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7002 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 18696 # number of LoadLockedReq misses
system.cpu0.dcache.demand_misses::cpu0.data 876974 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 151743 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1110663 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2139380 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 876974 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 151743 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1110663 # number of overall misses
system.cpu0.dcache.overall_misses::total 2139380 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2172880000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9444240500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 11617120500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1393922000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 14767149219 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 16161071219 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28928500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 105213000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 134141500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 3566802000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 24211389719 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 27778191719 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 3566802000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 24211389719 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 27778191719 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 4755127 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1201271 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 2969849 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8926247 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3369448 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 906524 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 1875965 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 6151937 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125950 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21468 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 55625 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 203043 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125392 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21336 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 52561 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 199289 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 8124575 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 2107795 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 4845814 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 15078184 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 8124575 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 2107795 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 4845814 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 15078184 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.148841 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086309 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.184407 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.152259 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050221 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.053019 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.300113 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.126835 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075435 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102152 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.125879 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092079 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.107941 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.071991 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229201 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.141886 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107941 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.071991 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229201 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.141886 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20957.561728 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17244.683299 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 8547.675773 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29001.976572 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26229.301528 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20711.807407 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13191.290470 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15026.135390 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7174.876979 # average LoadLockedReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23505.545561 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21799.042301 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 12984.225205 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23505.545561 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21799.042301 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12984.225205 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 420237 # number of cycles access was blocked
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu0.dcache.blocked_cycles::no_targets 580 # number of cycles access was blocked
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.blocked::no_mshrs 16818 # number of cycles access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.987335 # average number of cycles each access was blocked
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu0.dcache.avg_blocked_cycles::no_targets 82.857143 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.writebacks::writebacks 836144 # number of writebacks
system.cpu0.dcache.writebacks::total 836144 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 285747 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 285747 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 477794 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 477794 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1510 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1510 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 763541 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 763541 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 763541 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 763541 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 103680 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 261914 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 365594 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 48063 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85208 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 133271 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2193 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5492 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7685 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 151743 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 347122 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 498865 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 151743 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 347122 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 498865 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1965520000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4314581000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6280101000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1297796000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2151055620 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3448851620 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24542500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69880000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94422500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3263316000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6465636620 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 9728952620 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3263316000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6465636620 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 9728952620 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287578500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342019500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 629598000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357171000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 418642000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 775813000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644749500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 760661500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1405411000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086309 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088191 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040957 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053019 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045421 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021663 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102152 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098733 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037849 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.071991 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.033085 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.071991 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.033085 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18957.561728 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16473.273670 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17177.801058 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27001.976572 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25244.761290 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25878.485342 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11191.290470 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12723.962127 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12286.597267 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21505.545561 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18626.409793 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19502.175178 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21505.545561 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18626.409793 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19502.175178 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dtb.read_hits 1220324 # DTB read hits
system.cpu1.dtb.read_misses 1556 # DTB read misses
system.cpu1.dtb.read_acv 46 # DTB read access violations
system.cpu1.dtb.read_accesses 144016 # DTB read accesses
system.cpu1.dtb.write_hits 928239 # DTB write hits
system.cpu1.dtb.write_misses 207 # DTB write misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.write_acv 24 # DTB write access violations
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.dtb.write_accesses 60107 # DTB write accesses
system.cpu1.dtb.data_hits 2148563 # DTB hits
system.cpu1.dtb.data_misses 1763 # DTB misses
system.cpu1.dtb.data_acv 70 # DTB access violations
system.cpu1.dtb.data_accesses 204123 # DTB accesses
system.cpu1.itb.fetch_hits 875123 # ITB hits
system.cpu1.itb.fetch_misses 774 # ITB misses
system.cpu1.itb.fetch_acv 46 # ITB acv
system.cpu1.itb.fetch_accesses 875897 # ITB accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.numCycles 953544050 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu1.committedInsts 7861954 # Number of instructions committed
system.cpu1.committedOps 7861954 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 7314134 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 45433 # Number of float alu accesses
system.cpu1.num_func_calls 212083 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 960162 # number of instructions that are conditional controls
system.cpu1.num_int_insts 7314134 # number of integer instructions
system.cpu1.num_fp_insts 45433 # number of float instructions
system.cpu1.num_int_register_reads 10166177 # number of times the integer registers were read
system.cpu1.num_int_register_writes 5323216 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 24545 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 24803 # number of times the floating registers were written
system.cpu1.num_mem_refs 2156447 # number of memory refs
system.cpu1.num_load_insts 1225739 # Number of load instructions
system.cpu1.num_store_insts 930708 # Number of store instructions
system.cpu1.num_idle_cycles 195910529.325868 # Number of idle cycles
system.cpu1.num_busy_cycles 757633520.674132 # Number of busy cycles
system.cpu1.not_idle_fraction 0.794545 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.205455 # Percentage of idle cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu1.kern.mode_switch::user 0 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 0
system.cpu1.kern.mode_good::user 0
system.cpu1.kern.mode_good::idle 0
system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.branchPred.lookups 8412637 # Number of BP lookups
system.cpu2.branchPred.condPredicted 7718594 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 129281 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 6816710 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 5762098 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.branchPred.BTBHitPct 84.529018 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 288280 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 15520 # Number of incorrect RAS predictions.
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.dtb.read_hits 3230835 # DTB read hits
system.cpu2.dtb.read_misses 11458 # DTB read misses
system.cpu2.dtb.read_acv 112 # DTB read access violations
system.cpu2.dtb.read_accesses 217040 # DTB read accesses
system.cpu2.dtb.write_hits 2001660 # DTB write hits
system.cpu2.dtb.write_misses 2605 # DTB write misses
system.cpu2.dtb.write_acv 143 # DTB write access violations
system.cpu2.dtb.write_accesses 81606 # DTB write accesses
system.cpu2.dtb.data_hits 5232495 # DTB hits
system.cpu2.dtb.data_misses 14063 # DTB misses
system.cpu2.dtb.data_acv 255 # DTB access violations
system.cpu2.dtb.data_accesses 298646 # DTB accesses
system.cpu2.itb.fetch_hits 371714 # ITB hits
system.cpu2.itb.fetch_misses 5691 # ITB misses
system.cpu2.itb.fetch_acv 245 # ITB acv
system.cpu2.itb.fetch_accesses 377405 # ITB accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.write_acv 0 # DTB write access violations
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.data_hits 0 # DTB hits
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.numCycles 30535701 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.fetch.icacheStallCycles 8533986 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 34964689 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 8412637 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 6050378 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 8133499 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 621333 # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles 9684422 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 10316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 62496 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 78611 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 2608249 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 90274 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples 26910354 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.299302 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.309788 # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.fetch.rateDist::0 18776855 69.78% 69.78% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 272793 1.01% 70.79% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 440434 1.64% 72.43% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 4254201 15.81% 88.23% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 737771 2.74% 90.98% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 167398 0.62% 91.60% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 196636 0.73% 92.33% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 433593 1.61% 93.94% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 1630673 6.06% 100.00% # Number of instructions fetched each cycle (Total)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.fetch.rateDist::total 26910354 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.275502 # Number of branch fetches per cycle
system.cpu2.fetch.rate 1.145043 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 8661365 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 9779402 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 7537150 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 294171 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 392382 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 168927 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 12968 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 34563094 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 40757 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 392382 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 9017323 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 2819487 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 5795757 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 7393744 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 1245786 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 33400489 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 234346 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents 410991 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands 22419821 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 41624595 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 41459018 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 165577 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 20586998 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 1832823 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 505460 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 60216 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 3692928 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 3393863 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 2097985 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 374320 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 252386 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 30872998 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 630971 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 30415497 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 38395 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 2194504 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 1105046 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 445283 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 26910354 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.130253 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.565604 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.iq.issued_per_cycle::0 15319537 56.93% 56.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 3107474 11.55% 68.48% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 1555934 5.78% 74.26% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 5075643 18.86% 93.12% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 913365 3.39% 96.51% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 492006 1.83% 98.34% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 286832 1.07% 99.41% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 141760 0.53% 99.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 17803 0.07% 100.00% # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.iq.issued_per_cycle::total 26910354 # Number of insts issued each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.iq.fu_full::IntAlu 34989 13.90% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 113310 45.00% 58.89% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 103504 41.11% 100.00% # attempts to use FU when none available
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.iq.FU_type_0::No_OpClass 2444 0.01% 0.01% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 24705605 81.23% 81.24% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 20302 0.07% 81.30% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.30% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 8486 0.03% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 1222 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 3362289 11.05% 92.39% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 2024695 6.66% 99.05% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 290454 0.95% 100.00% # Type of FU issued
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.iq.FU_type_0::total 30415497 # Type of FU issued
system.cpu2.iq.rate 0.996063 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 251803 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.008279 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 87793643 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 33586183 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 30009832 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 237903 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 116334 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 112629 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 30540939 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 123917 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 191281 # Number of loads that had data forwarded from stores
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.iew.lsq.thread0.squashedLoads 420182 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 991 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 4150 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 166078 # Number of stores squashed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.iew.lsq.thread0.rescheduledLoads 4737 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 23355 # Number of times an access to memory failed due to the cache being blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.iew.iewSquashCycles 392382 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 2039220 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 211536 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 32790346 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 224393 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 3393863 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 2097985 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 560382 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 2248 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 4150 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 66680 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 129830 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 196510 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 30250738 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 3250585 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 164759 # Number of squashed instructions skipped in execute
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iew.exec_swp 0 # number of swp insts executed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.iew.exec_nop 1286377 # number of nop insts executed
system.cpu2.iew.exec_refs 5259361 # number of memory reference insts executed
system.cpu2.iew.exec_branches 6817854 # Number of branches executed
system.cpu2.iew.exec_stores 2008776 # Number of stores executed
system.cpu2.iew.exec_rate 0.990668 # Inst execution rate
system.cpu2.iew.wb_sent 30155470 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 30122461 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 17393526 # num instructions producing a value
system.cpu2.iew.wb_consumers 20640191 # num instructions consuming a value
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.iew.wb_rate 0.986467 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.842702 # average fanout of values written-back
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.commit.commitSquashedInsts 2374784 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 185688 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 182288 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 26517972 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.145282 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.851176 # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.commit.committed_per_cycle::0 16375650 61.75% 61.75% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 2329506 8.78% 70.54% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1218962 4.60% 75.13% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 4807374 18.13% 93.26% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 502647 1.90% 95.16% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 186920 0.70% 95.86% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 179412 0.68% 96.54% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 180660 0.68% 97.22% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 736841 2.78% 100.00% # Number of insts commited each cycle
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.commit.committed_per_cycle::total 26517972 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 30370560 # Number of instructions committed
system.cpu2.commit.committedOps 30370560 # Number of ops (including micro ops) committed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.commit.refs 4905588 # Number of memory references committed
system.cpu2.commit.loads 2973681 # Number of loads committed
system.cpu2.commit.membars 65235 # Number of memory barriers committed
system.cpu2.commit.branches 6667985 # Number of branches committed
system.cpu2.commit.fp_insts 111312 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 28908362 # Number of committed integer instructions.
system.cpu2.commit.function_calls 232233 # Number of function calls committed.
system.cpu2.commit.bw_lim_events 736841 # number cycles where commit BW limit reached
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu2.rob.rob_reads 58454827 # The number of ROB reads
system.cpu2.rob.rob_writes 65882898 # The number of ROB writes
system.cpu2.timesIdled 242873 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 3625347 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 1745288097 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 29192891 # Number of Instructions Simulated
system.cpu2.committedOps 29192891 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 29192891 # Number of Instructions Simulated
system.cpu2.cpi 1.045998 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.045998 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.956025 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.956025 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 39779581 # number of integer regfile reads
system.cpu2.int_regfile_writes 21289103 # number of integer regfile writes
system.cpu2.fp_regfile_reads 68643 # number of floating regfile reads
system.cpu2.fp_regfile_writes 68941 # number of floating regfile writes
system.cpu2.misc_regfile_reads 4607989 # number of misc regfile reads
system.cpu2.misc_regfile_writes 260558 # number of misc regfile writes
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu2.kern.mode_switch::user 0 # number of protection mode switches
system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu2.kern.mode_good::kernel 0
system.cpu2.kern.mode_good::user 0
system.cpu2.kern.mode_good::idle 0
system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu2.kern.swap_context 0 # number of times the context was actually changed
---------- End Simulation Statistics ----------
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