gem5/src/arch/mips/isa/base.isa

// -*- mode:c++ -*-

////////////////////////////////////////////////////////////////////
//
// Base class for MIPS instructions, and some support functions
//

//Outputs to decoder.hh
output header {{

    using namespace MipsISA;


    /**
     * Base class for all MIPS static instructions.
     */
    class MipsStaticInst : public StaticInst
    {
      protected:

        // Constructor
        MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
            : StaticInst(mnem, _machInst, __opClass)
        {
        }

        /// Print a register name for disassembly given the unique
        /// dependence tag number (FP or int).
        void printReg(std::ostream &os, int reg) const;

        std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };

}};

//Ouputs to decoder.cc
output decoder {{

    void MipsStaticInst::printReg(std::ostream &os, int reg) const
    {
        if (reg < FP_Base_DepTag) {
            ccprintf(os, "r%d", reg);
        }
        else {
            ccprintf(os, "f%d", reg - FP_Base_DepTag);
        }
    }

    std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
        std::stringstream ss;

        ccprintf(ss, "%-10s ", mnemonic);

        if(_numDestRegs > 0){
            printReg(ss, _destRegIdx[0]);
        }

        if(_numSrcRegs > 0) {
            ss << ", ";
            printReg(ss, _srcRegIdx[0]);
        }

        if(_numSrcRegs > 1) {
            ss << ", ";
            printReg(ss, _srcRegIdx[1]);
        }


        if(mnemonic == "sll" || mnemonic == "sra"){
            ccprintf(ss,", %d",SA);
        }

        return ss.str();
    }

}};