2014-10-30 05:18:29 +01:00
|
|
|
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
2011-03-18 01:20:22 +01:00
|
|
|
warn: Sockets disabled, not accepting vnc client connections
|
|
|
|
warn: Sockets disabled, not accepting terminal connections
|
|
|
|
warn: Sockets disabled, not accepting gdb connections
|
2014-10-11 23:18:51 +02:00
|
|
|
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
2014-10-30 05:18:29 +01:00
|
|
|
warn: Not doing anything for miscreg ACTLR
|
|
|
|
warn: Not doing anything for write of miscreg ACTLR
|
2011-03-18 01:20:22 +01:00
|
|
|
warn: The clidr register always reports 0 caches.
|
2011-07-15 18:53:35 +02:00
|
|
|
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
|
2011-03-18 01:20:22 +01:00
|
|
|
warn: The csselr register isn't implemented.
|
2014-10-30 05:18:29 +01:00
|
|
|
warn: instruction 'mcr dccmvau' unimplemented
|
|
|
|
warn: instruction 'mcr icimvau' unimplemented
|
2011-08-19 22:08:09 +02:00
|
|
|
warn: instruction 'mcr bpiallis' unimplemented
|
|
|
|
warn: instruction 'mcr icialluis' unimplemented
|
2011-03-18 01:20:22 +01:00
|
|
|
warn: instruction 'mcr dccimvac' unimplemented
|
2014-10-30 05:18:29 +01:00
|
|
|
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
|
|
|
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
|
|
|
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
|
|
|
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
|
|
|
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
|
|
|
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
|
|
|
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
|
|
|
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
|
|
|
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
|
|
|
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
|
|
|
|
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
|
|
|
|
warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
|
|
|
|
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
|
|
|
|
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
|
|
|
|
warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
|
|
|
|
warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
|
|
|
|
warn: Returning zero for read from miscreg pmcr
|
|
|
|
warn: Ignoring write to miscreg pmcntenclr
|
|
|
|
warn: Ignoring write to miscreg pmintenclr
|
|
|
|
warn: Ignoring write to miscreg pmovsr
|
|
|
|
warn: Ignoring write to miscreg pmcr
|
|
|
|
warn: instruction 'mcr dcisw' unimplemented
|
2015-04-23 05:22:29 +02:00
|
|
|
warn: instruction 'mcr bpiall' unimplemented
|