gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini

[root]
type=Root
children=system
full_system=true
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000

[system]
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
boot_loader=/projects/pd/randd/dist/binaries/boot.arm
boot_loader_mem=system.realview.nvmem
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
memories=system.physmem system.realview.nvmem
midr_regval=890224640
num_work_ids=16
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]

[system.bridge]
type=Bridge
delay=50000
nack_delay=4000
ranges=268435456:520093695 1073741824:1610612735
req_size=16
resp_size=16
write_ack=false
master=system.iobus.slave[0]
slave=system.membus.master[0]

[system.cf0]
type=IdeDisk
children=image
delay=1000000
driveID=master
image=system.cf0.image

[system.cf0.image]
type=CowDiskImage
children=child
child=system.cf0.image.child
image_file=
read_only=false
table_size=65536

[system.cf0.image.child]
type=RawDiskImage
image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
read_only=true

[system.cpu0]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu0.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu0.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu0.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu0.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side

[system.cpu0.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.slave[1]

[system.cpu0.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu0.dtb.walker

[system.cpu0.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.toL2Bus.slave[3]

[system.cpu0.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8

[system.cpu0.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu0.fuPool.FUList0.opList

[system.cpu0.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1

[system.cpu0.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1

[system.cpu0.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3

[system.cpu0.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20

[system.cpu0.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2

[system.cpu0.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2

[system.cpu0.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2

[system.cpu0.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2

[system.cpu0.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2

[system.cpu0.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4

[system.cpu0.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12

[system.cpu0.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24

[system.cpu0.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu0.fuPool.FUList4.opList

[system.cpu0.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1

[system.cpu0.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19

[system.cpu0.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1

[system.cpu0.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1

[system.cpu0.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1

[system.cpu0.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1

[system.cpu0.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1

[system.cpu0.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1

[system.cpu0.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1

[system.cpu0.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1

[system.cpu0.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1

[system.cpu0.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1

[system.cpu0.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1

[system.cpu0.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1

[system.cpu0.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1

[system.cpu0.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1

[system.cpu0.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1

[system.cpu0.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1

[system.cpu0.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1

[system.cpu0.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1

[system.cpu0.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1

[system.cpu0.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1

[system.cpu0.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu0.fuPool.FUList6.opList

[system.cpu0.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1

[system.cpu0.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1

[system.cpu0.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1

[system.cpu0.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1

[system.cpu0.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu0.fuPool.FUList8.opList

[system.cpu0.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3

[system.cpu0.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.slave[0]

[system.cpu0.interrupts]
type=ArmInterrupts

[system.cpu0.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu0.itb.walker

[system.cpu0.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.toL2Bus.slave[2]

[system.cpu0.tracer]
type=ExeTracer

[system.cpu1]
type=DerivO3CPU
children=dcache dtb fuPool icache interrupts itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu1.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu1.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu1.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
phase=0
predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
system=system
tracer=system.cpu1.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side

[system.cpu1.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.slave[5]

[system.cpu1.dtb]
type=ArmTLB
children=walker
size=64
walker=system.cpu1.dtb.walker

[system.cpu1.dtb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.toL2Bus.slave[7]

[system.cpu1.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8

[system.cpu1.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu1.fuPool.FUList0.opList

[system.cpu1.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1

[system.cpu1.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1

[system.cpu1.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3

[system.cpu1.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20

[system.cpu1.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2

[system.cpu1.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2

[system.cpu1.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2

[system.cpu1.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2

[system.cpu1.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2

[system.cpu1.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4

[system.cpu1.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12

[system.cpu1.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24

[system.cpu1.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu1.fuPool.FUList4.opList

[system.cpu1.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1

[system.cpu1.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19

[system.cpu1.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1

[system.cpu1.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1

[system.cpu1.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1

[system.cpu1.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1

[system.cpu1.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1

[system.cpu1.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1

[system.cpu1.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1

[system.cpu1.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1

[system.cpu1.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1

[system.cpu1.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1

[system.cpu1.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1

[system.cpu1.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1

[system.cpu1.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1

[system.cpu1.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1

[system.cpu1.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1

[system.cpu1.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1

[system.cpu1.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1

[system.cpu1.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1

[system.cpu1.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1

[system.cpu1.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1

[system.cpu1.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu1.fuPool.FUList6.opList

[system.cpu1.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1

[system.cpu1.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1

[system.cpu1.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1

[system.cpu1.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1

[system.cpu1.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu1.fuPool.FUList8.opList

[system.cpu1.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3

[system.cpu1.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.slave[4]

[system.cpu1.interrupts]
type=ArmInterrupts

[system.cpu1.itb]
type=ArmTLB
children=walker
size=64
walker=system.cpu1.itb.walker

[system.cpu1.itb.walker]
type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
port=system.toL2Bus.slave[6]

[system.cpu1.tracer]
type=ExeTracer

[system.intrctrl]
type=IntrControl
sys=system

[system.iobus]
type=Bus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma

[system.iocache]
type=BaseCache
addr_ranges=0:268435455
assoc=8
block_size=64
forward_snoops=false
hash_delay=1
is_top_level=false
latency=50000
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[1]

[system.l2c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
forward_snoops=true
hash_delay=1
is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]

[system.membus]
type=Bus
children=badaddr_responder
block_size=64
bus_id=1
clock=1000
header_cycles=1
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
slave=system.system_port system.iocache.mem_side system.l2c.mem_side

[system.membus.badaddr_responder]
type=IsaFake
fake_mem=false
pio_addr=0
pio_latency=1000
pio_size=8
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=warn
pio=system.membus.default

[system.physmem]
type=PhysicalMemory
file=
latency=30000
latency_var=0
null=false
range=0:134217727
zero=false
port=system.membus.master[2]

[system.realview]
type=RealView
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
max_mem_size=268435456
mem_start_addr=0
pci_cfg_base=0
system=system

[system.realview.a9scu]
type=A9SCU
pio_addr=520093696
pio_latency=1000
system=system
pio=system.membus.master[5]

[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268451840
pio_latency=1000
system=system
pio=system.iobus.master[21]

[system.realview.cf_ctrl]
type=IdeController
BAR0=402653184
BAR0LegacyIO=true
BAR0Size=16
BAR1=402653440
BAR1LegacyIO=true
BAR1Size=1
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
BAR3=1
BAR3LegacyIO=false
BAR3Size=4
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
CardbusCIS=0
ClassCode=1
Command=1
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
MaximumLatency=0
MinimumGrant=0
ProgIF=133
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
config_latency=20000
ctrl_offset=2
disks=system.cf0
io_shift=1
max_backoff_delay=10000000
min_backoff_delay=4000
pci_bus=2
pci_dev=7
pci_func=0
pio_latency=1000
platform=system.realview
system=system
config=system.iobus.master[8]
dma=system.iobus.slave[2]
pio=system.iobus.master[7]

[system.realview.clcd]
type=Pl111
amba_id=1315089
clock=41667
gic=system.realview.gic
int_num=55
max_backoff_delay=10000000
min_backoff_delay=4000
pio_addr=268566528
pio_latency=10000
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]

[system.realview.dmac_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268632064
pio_latency=1000
system=system
pio=system.iobus.master[9]

[system.realview.flash_fake]
type=IsaFake
fake_mem=true
pio_addr=1073741824
pio_latency=1000
pio_size=536870912
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[24]

[system.realview.gic]
type=Gic
cpu_addr=520093952
cpu_pio_delay=10000
dist_addr=520097792
dist_pio_delay=10000
int_latency=10000
it_lines=128
platform=system.realview
system=system
pio=system.membus.master[3]

[system.realview.gpio0_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268513280
pio_latency=1000
system=system
pio=system.iobus.master[16]

[system.realview.gpio1_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268517376
pio_latency=1000
system=system
pio=system.iobus.master[17]

[system.realview.gpio2_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268521472
pio_latency=1000
system=system
pio=system.iobus.master[18]

[system.realview.kmi0]
type=Pl050
amba_id=1314896
gic=system.realview.gic
int_delay=1000000
int_num=52
is_mouse=false
pio_addr=268460032
pio_latency=1000
system=system
vnc=system.vncserver
pio=system.iobus.master[5]

[system.realview.kmi1]
type=Pl050
amba_id=1314896
gic=system.realview.gic
int_delay=1000000
int_num=53
is_mouse=true
pio_addr=268464128
pio_latency=1000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]

[system.realview.l2x0_fake]
type=IsaFake
fake_mem=false
pio_addr=520101888
pio_latency=1000
pio_size=4095
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.membus.master[4]

[system.realview.local_cpu_timer]
type=CpuLocalTimer
clock=1000
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
pio_addr=520095232
pio_latency=1000
system=system
pio=system.membus.master[6]

[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268455936
pio_latency=1000
system=system
pio=system.iobus.master[22]

[system.realview.nvmem]
type=PhysicalMemory
file=
latency=30000
latency_var=0
null=false
range=2147483648:2214592511
zero=true
port=system.membus.master[1]

[system.realview.realview_io]
type=RealViewCtrl
idreg=0
pio_addr=268435456
pio_latency=1000
proc_id0=201326592
proc_id1=201327138
system=system
pio=system.iobus.master[1]

[system.realview.rtc]
type=PL031
amba_id=3412017
gic=system.realview.gic
int_delay=100000
int_num=42
pio_addr=268529664
pio_latency=1000
system=system
time=Thu Jan  1 00:00:00 2009
pio=system.iobus.master[23]

[system.realview.sci_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268492800
pio_latency=1000
system=system
pio=system.iobus.master[20]

[system.realview.smc_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=269357056
pio_latency=1000
system=system
pio=system.iobus.master[13]

[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
ignore_access=true
pio_addr=268439552
pio_latency=1000
system=system
pio=system.iobus.master[14]

[system.realview.ssp_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268488704
pio_latency=1000
system=system
pio=system.iobus.master[19]

[system.realview.timer0]
type=Sp804
amba_id=1316868
clock0=1000000
clock1=1000000
gic=system.realview.gic
int_num0=36
int_num1=36
pio_addr=268505088
pio_latency=1000
system=system
pio=system.iobus.master[2]

[system.realview.timer1]
type=Sp804
amba_id=1316868
clock0=1000000
clock1=1000000
gic=system.realview.gic
int_num0=37
int_num1=37
pio_addr=268509184
pio_latency=1000
system=system
pio=system.iobus.master[3]

[system.realview.uart]
type=Pl011
end_on_eot=false
gic=system.realview.gic
int_delay=100000
int_num=44
pio_addr=268472320
pio_latency=1000
platform=system.realview
system=system
terminal=system.terminal
pio=system.iobus.master[0]

[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268476416
pio_latency=1000
system=system
pio=system.iobus.master[10]

[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268480512
pio_latency=1000
system=system
pio=system.iobus.master[11]

[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268484608
pio_latency=1000
system=system
pio=system.iobus.master[12]

[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
ignore_access=false
pio_addr=268500992
pio_latency=1000
system=system
pio=system.iobus.master[15]

[system.terminal]
type=Terminal
intr_control=system.intrctrl
number=0
output=true
port=3456

[system.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port

[system.vncserver]
type=VncServer
frame_capture=false
number=0
port=5900