2007-03-03 17:01:48 +01:00
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/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* Redistribution and use of this software in source and binary forms,
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* with or without modification, are permitted provided that the
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* following conditions are met:
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*
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* The software must be used only for Non-Commercial Use which means any
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* use which is NOT directed to receiving any direct monetary
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* compensation for, or commercial advantage from such use. Illustrative
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* examples of non-commercial use are academic research, personal study,
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* teaching, education and corporate research & development.
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* Illustrative examples of commercial use are distributing products for
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* commercial advantage and providing services using the software for
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* commercial advantage.
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*
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* If you wish to use this software or functionality therein that may be
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* covered by patents for commercial use, please contact:
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* Director of Intellectual Property Licensing
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* Office of Strategy and Technology
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* Hewlett-Packard Company
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* 1501 Page Mill Road
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* Palo Alto, California 94304
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*
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* Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer. Redistributions
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* in binary form must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution. Neither the name of
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* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission. No right of
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* sublicense is granted herewith. Derivatives of the software and
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* output created using the software may be prepared, but only for
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* Non-Commercial Uses. Derivatives of the software may be shared with
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* others provided: (i) the others agree to abide by the list of
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* conditions herein which includes the Non-Commercial Use restrictions;
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* and (ii) such Derivatives of the software include the above copyright
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* notice to acknowledge the contribution from this software where
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* applicable, this list of conditions and the disclaimer below.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_TYPES_HH__
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#define __ARCH_X86_TYPES_HH__
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2007-03-05 15:53:51 +01:00
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#include <inttypes.h>
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2007-03-15 03:47:42 +01:00
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#include <iostream>
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2007-03-05 15:53:51 +01:00
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2007-03-21 20:19:53 +01:00
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#include "base/bitfield.hh"
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#include "base/cprintf.hh"
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2007-03-03 17:01:48 +01:00
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namespace X86ISA
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{
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2007-03-13 17:13:21 +01:00
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//This really determines how many bytes are passed to the predecoder.
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typedef uint64_t MachInst;
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2007-03-15 03:47:42 +01:00
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enum Prefixes {
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2007-04-06 17:19:23 +02:00
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NoOverride,
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CSOverride,
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DSOverride,
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ESOverride,
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FSOverride,
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GSOverride,
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SSOverride,
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RexPrefix,
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OperandSizeOverride,
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AddressSizeOverride,
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Lock,
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Rep,
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Repne
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};
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BitUnion8(LegacyPrefixVector)
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Bitfield<7> repne;
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Bitfield<6> rep;
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Bitfield<5> lock;
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Bitfield<4> addr;
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Bitfield<3> op;
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2007-03-15 03:47:42 +01:00
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//There can be only one segment override, so they share the
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//first 3 bits in the legacyPrefixes bitfield.
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2007-04-06 17:19:23 +02:00
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Bitfield<2,0> seg;
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EndBitUnion(LegacyPrefixVector)
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2007-03-15 03:47:42 +01:00
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2007-03-21 20:19:53 +01:00
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BitUnion8(ModRM)
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Bitfield<7,6> mod;
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Bitfield<5,3> reg;
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Bitfield<2,0> rm;
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EndBitUnion(ModRM)
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BitUnion8(Sib)
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Bitfield<7,6> scale;
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Bitfield<5,3> index;
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Bitfield<2,0> base;
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EndBitUnion(Sib)
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BitUnion8(Rex)
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Bitfield<3> w;
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Bitfield<2> r;
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Bitfield<1> x;
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Bitfield<0> b;
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EndBitUnion(Rex)
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BitUnion8(Opcode)
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Bitfield<7,3> top5;
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Bitfield<2,0> bottom3;
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EndBitUnion(Opcode)
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2007-03-13 17:13:21 +01:00
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//The intermediate structure the x86 predecoder returns.
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struct ExtMachInst
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{
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2007-03-21 20:19:53 +01:00
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//Prefixes
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2007-04-06 17:19:23 +02:00
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LegacyPrefixVector legacy;
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2007-03-21 20:19:53 +01:00
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Rex rex;
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//This holds all of the bytes of the opcode
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struct
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{
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//The number of bytes in this opcode. Right now, we ignore that
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//this can be 3 in some cases
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uint8_t num;
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//The first byte detected in a 2+ byte opcode. Should be 0xF0.
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uint8_t prefixA;
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//The second byte detected in a 3+ byte opcode. Could be 0xF0 for
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//3dnow instructions, or 0x38-0x3F for some SSE instructions.
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uint8_t prefixB;
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//The main opcode byte. The highest addressed byte in the opcode.
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Opcode op;
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} opcode;
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//Modifier bytes
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ModRM modRM;
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uint8_t sib;
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//Immediate fields
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2007-03-15 03:47:42 +01:00
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uint64_t immediate;
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uint64_t displacement;
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2007-04-06 17:19:23 +02:00
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//The effective operand size.
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uint8_t opSize;
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2007-06-12 18:23:42 +02:00
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//The effective address size.
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uint8_t addrSize;
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2007-03-13 17:13:21 +01:00
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};
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2007-03-15 03:47:42 +01:00
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inline static std::ostream &
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operator << (std::ostream & os, const ExtMachInst & emi)
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{
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2007-03-21 20:19:53 +01:00
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ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
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"op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t"
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"prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t"
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"modRM = %#x,\n\tsib = %#x,\n\t"
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"immediate = %#x,\n\tdisplacement = %#x\n}\n",
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emi.legacy, (uint8_t)emi.rex,
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emi.opcode.num, emi.opcode.op,
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emi.opcode.prefixA, emi.opcode.prefixB,
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(uint8_t)emi.modRM, (uint8_t)emi.sib,
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emi.immediate, emi.displacement);
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2007-03-15 03:47:42 +01:00
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return os;
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}
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inline static bool
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operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
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2007-03-13 17:13:21 +01:00
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{
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2007-04-04 16:27:00 +02:00
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if(emi1.legacy != emi2.legacy)
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return false;
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if(emi1.rex != emi2.rex)
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return false;
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if(emi1.opcode.num != emi2.opcode.num)
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return false;
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if(emi1.opcode.op != emi2.opcode.op)
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return false;
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if(emi1.opcode.prefixA != emi2.opcode.prefixA)
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return false;
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if(emi1.opcode.prefixB != emi2.opcode.prefixB)
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return false;
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if(emi1.modRM != emi2.modRM)
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return false;
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if(emi1.sib != emi2.sib)
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return false;
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if(emi1.immediate != emi2.immediate)
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return false;
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if(emi1.displacement != emi2.displacement)
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return false;
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2007-03-13 17:13:21 +01:00
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return true;
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}
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2007-03-03 18:19:52 +01:00
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typedef uint64_t IntReg;
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2007-03-05 17:10:11 +01:00
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//XXX Should this be a 128 bit structure for XMM memory ops?
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typedef uint64_t LargestRead;
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2007-03-03 18:19:52 +01:00
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typedef uint64_t MiscReg;
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//These floating point types are correct for mmx, but not
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//technically for x87 (80 bits) or at all for xmm (128 bits)
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typedef double FloatReg;
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typedef uint64_t FloatRegBits;
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typedef union
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{
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IntReg intReg;
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FloatReg fpReg;
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MiscReg ctrlReg;
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} AnyReg;
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//XXX This is very hypothetical. X87 instructions would need to
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//change their "context" constantly. It's also not clear how
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//this would be handled as far as out of order execution.
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//Maybe x87 instructions are in order?
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enum RegContextParam
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{
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CONTEXT_X87_TOP
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};
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typedef int RegContextVal;
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typedef uint8_t RegIndex;
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2007-03-03 17:01:48 +01:00
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};
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#endif // __ARCH_X86_TYPES_HH__
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