gem5/tests/configs/tsunami-simple-timing.py

# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Authors: Steve Reinhardt

import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig


# --------------------
# Base L1 Cache
# ====================

class L1(BaseCache):
    hit_latency = 2
    response_latency = 2
    block_size = 64
    mshrs = 4
    tgts_per_mshr = 8
    is_top_level = True

# ----------------------
# Base L2 Cache
# ----------------------

class L2(BaseCache):
    block_size = 64
    hit_latency = 20
    response_latency = 20
    mshrs = 92
    tgts_per_mshr = 16
    write_buffers = 8

# ---------------------
# I/O Cache
# ---------------------
class IOCache(BaseCache):
    assoc = 8
    block_size = 64
    hit_latency = 50
    response_latency = 50
    mshrs = 20
    size = '1kB'
    tgts_per_mshr = 12
    addr_ranges = [AddrRange(0, size='8GB')]
    forward_snoops = False
    is_top_level = True

#cpu
cpu = TimingSimpleCPU(cpu_id=0)
#the system
system = FSConfig.makeLinuxAlphaSystem('timing')

system.cpu = cpu

#create the iocache
system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave

#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
                              L1(size = '32kB', assoc = 4),
                              L2(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system
cpu.connectAllPorts(system.membus)
# set the cpu clock along with the caches and l1-l2 bus
cpu.clock = '2GHz'

root = Root(full_system=True, system=system)
m5.ticks.setGlobalFrequency('1THz')