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gem5/configs/test/fs.py

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make ide disk work for newmem SConscript: compile ide devices base/chunk_generator.hh: add another parameter to the chuck generator called complete() which returns the number of bytes transfered so far. Very useful for adding to a pointer. configs/test/fs.py: Add ide disk to fs test configuration dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: update for new memory system mem/bus.cc: support devices that return multiple ranges remove old ranges before using new info mem/packet.hh: make senderstate void* per steve's request that we use every construct possible in C++ mem/physical.cc: have memory stamp the packet with the time. mem/physical.hh: actually set the memory latency variable python/m5/objects/Device.py: Add DmaDevice python/m5/objects/Ide.py: Ide disk no longer has a physmem pointer python/m5/objects/Pci.py: update pci device for newmem python/m5/objects/PhysicalMemory.py: add latency parameter for physical memory sim/byteswap.hh: use fast architecture dependent byteswap calls if they exist --HG-- extra : convert_revision : e3cf2e8f61064ad302d94bc22010a00c59f3f793
2006-04-20 23:14:30 +02:00
from m5 import *
fs now gets to the point where it would really like a filesystem. Time to make the ide device work arch/alpha/system.cc: write the machine type and rev in the correct place cpu/simple/cpu.cc: reset the packet structure every time it's reused... wow the simple cpu code for talking to memory is getting horrible. dev/alpha_console.cc: move the setAlphaAccess to startup() to make sure that the console binary is loaded dev/tsunami_cchip.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: fix a couple of bugs injected in the newmem fixes mem/bus.cc: More verbose bus tracing mem/packet.hh: Add a constructor to packet to set the result to unknown and a reset method in the case it's being reused mem/vport.hh: don't need are own read/write methods since the base functional port ones call writeBlob readBlob which do the translation for us --HG-- extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 23:46:25 +02:00
import os
from SysPaths import *
# Base for tests is directory containing this file.
test_base = os.path.dirname(__file__)
make ide disk work for newmem SConscript: compile ide devices base/chunk_generator.hh: add another parameter to the chuck generator called complete() which returns the number of bytes transfered so far. Very useful for adding to a pointer. configs/test/fs.py: Add ide disk to fs test configuration dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: update for new memory system mem/bus.cc: support devices that return multiple ranges remove old ranges before using new info mem/packet.hh: make senderstate void* per steve's request that we use every construct possible in C++ mem/physical.cc: have memory stamp the packet with the time. mem/physical.hh: actually set the memory latency variable python/m5/objects/Device.py: Add DmaDevice python/m5/objects/Ide.py: Ide disk no longer has a physmem pointer python/m5/objects/Pci.py: update pci device for newmem python/m5/objects/PhysicalMemory.py: add latency parameter for physical memory sim/byteswap.hh: use fast architecture dependent byteswap calls if they exist --HG-- extra : convert_revision : e3cf2e8f61064ad302d94bc22010a00c59f3f793
2006-04-20 23:14:30 +02:00
linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
class IdeControllerPciData(PciConfigData):
VendorID = 0x8086
DeviceID = 0x7111
Command = 0x0
Status = 0x280
Revision = 0x0
ClassCode = 0x01
SubClassCode = 0x01
ProgIF = 0x85
BAR0 = 0x00000001
BAR1 = 0x00000001
BAR2 = 0x00000001
BAR3 = 0x00000001
BAR4 = 0x00000001
BAR5 = 0x00000001
InterruptLine = 0x1f
InterruptPin = 0x01
BAR0Size = '8B'
BAR1Size = '4B'
BAR2Size = '8B'
BAR3Size = '4B'
BAR4Size = '16B'
Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working after merge from head. Checkpointing may need some work now. Endian-happiness still not complete. SConscript: add all devices back into make file base/inet.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/pktfifo.cc: dev/pktfifo.hh: rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system configs/test/fs.py: add nics to fs.py cpu/cpu_exec_context.cc: remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the static virtual ports in the exec context cpu/simple/cpu.cc: cpu/simple/cpu.hh: dev/alpha_console.cc: dev/ide_ctrl.cc: use new methods for accessing packet data dev/ide_disk.cc: add some more dprintfs dev/io_device.cc: delete packets when we are done with them. Update for new packet methods to access data dev/isa_fake.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: dev/uart8250.hh: mem/physical.cc: mem/port.cc: dUpdate for new packet methods to access data dev/ns_gige.cc: Update for new memory system dev/ns_gige.hh: python/m5/objects/Ethernet.py: update for new memory system dev/sinic.cc: dev/sinic.hh: Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions mem/packet.hh: Add methods to access data instead of accessing it directly. --HG-- extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-25 01:31:50 +02:00
class SinicPciData(PciConfigData):
VendorID = 0x1291
DeviceID = 0x1293
Status = 0x0290
SubClassCode = 0x00
ClassCode = 0x02
ProgIF = 0x00
BAR0 = 0x00000000
BAR1 = 0x00000000
BAR2 = 0x00000000
BAR3 = 0x00000000
BAR4 = 0x00000000
BAR5 = 0x00000000
MaximumLatency = 0x34
MinimumGrant = 0xb0
InterruptLine = 0x1e
InterruptPin = 0x01
BAR0Size = '64kB'
class NSGigEPciData(PciConfigData):
VendorID = 0x100B
DeviceID = 0x0022
Status = 0x0290
SubClassCode = 0x00
ClassCode = 0x02
ProgIF = 0x00
BAR0 = 0x00000001
BAR1 = 0x00000000
BAR2 = 0x00000000
BAR3 = 0x00000000
BAR4 = 0x00000000
BAR5 = 0x00000000
MaximumLatency = 0x34
MinimumGrant = 0xb0
InterruptLine = 0x1e
InterruptPin = 0x01
BAR0Size = '256B'
BAR1Size = '4kB'
make ide disk work for newmem SConscript: compile ide devices base/chunk_generator.hh: add another parameter to the chuck generator called complete() which returns the number of bytes transfered so far. Very useful for adding to a pointer. configs/test/fs.py: Add ide disk to fs test configuration dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: update for new memory system mem/bus.cc: support devices that return multiple ranges remove old ranges before using new info mem/packet.hh: make senderstate void* per steve's request that we use every construct possible in C++ mem/physical.cc: have memory stamp the packet with the time. mem/physical.hh: actually set the memory latency variable python/m5/objects/Device.py: Add DmaDevice python/m5/objects/Ide.py: Ide disk no longer has a physmem pointer python/m5/objects/Pci.py: update pci device for newmem python/m5/objects/PhysicalMemory.py: add latency parameter for physical memory sim/byteswap.hh: use fast architecture dependent byteswap calls if they exist --HG-- extra : convert_revision : e3cf2e8f61064ad302d94bc22010a00c59f3f793
2006-04-20 23:14:30 +02:00
class LinuxRootDisk(IdeDisk):
raw_image = RawDiskImage(image_file=linux_image, read_only=True)
image = CowDiskImage(child=Parent.raw_image, read_only=False)
class LinuxSwapDisk(IdeDisk):
raw_image = RawDiskImage(image_file = disk('linux-bigswap2.img'),
read_only=True)
image = CowDiskImage(child = Parent.raw_image, read_only=False)
class SpecwebFilesetDisk(IdeDisk):
raw_image = RawDiskImage(image_file = disk('specweb-fileset.img'),
read_only=True)
image = CowDiskImage(child = Parent.raw_image, read_only=False)
fs now gets to the point where it would really like a filesystem. Time to make the ide device work arch/alpha/system.cc: write the machine type and rev in the correct place cpu/simple/cpu.cc: reset the packet structure every time it's reused... wow the simple cpu code for talking to memory is getting horrible. dev/alpha_console.cc: move the setAlphaAccess to startup() to make sure that the console binary is loaded dev/tsunami_cchip.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: fix a couple of bugs injected in the newmem fixes mem/bus.cc: More verbose bus tracing mem/packet.hh: Add a constructor to packet to set the result to unknown and a reset method in the case it's being reused mem/vport.hh: don't need are own read/write methods since the base functional port ones call writeBlob readBlob which do the translation for us --HG-- extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 23:46:25 +02:00
class BaseTsunami(Tsunami):
cchip = TsunamiCChip(pio_addr=0x801a0000000)
pchip = TsunamiPChip(pio_addr=0x80180000000)
pciconfig = PciConfigAll(pio_addr=0x801fe000000)
fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
fake_ata1 = IsaFake(pio_addr=0x801fc000170)
fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
io = TsunamiIO(pio_addr=0x801fc000000)
uart = Uart8250(pio_addr=0x801fc0003f8)
Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working after merge from head. Checkpointing may need some work now. Endian-happiness still not complete. SConscript: add all devices back into make file base/inet.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/pktfifo.cc: dev/pktfifo.hh: rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system configs/test/fs.py: add nics to fs.py cpu/cpu_exec_context.cc: remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the static virtual ports in the exec context cpu/simple/cpu.cc: cpu/simple/cpu.hh: dev/alpha_console.cc: dev/ide_ctrl.cc: use new methods for accessing packet data dev/ide_disk.cc: add some more dprintfs dev/io_device.cc: delete packets when we are done with them. Update for new packet methods to access data dev/isa_fake.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: dev/uart8250.hh: mem/physical.cc: mem/port.cc: dUpdate for new packet methods to access data dev/ns_gige.cc: Update for new memory system dev/ns_gige.hh: python/m5/objects/Ethernet.py: update for new memory system dev/sinic.cc: dev/sinic.hh: Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions mem/packet.hh: Add methods to access data instead of accessing it directly. --HG-- extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-25 01:31:50 +02:00
ethernet = NSGigE(configdata=NSGigEPciData(),
pci_bus=0, pci_dev=1, pci_func=0)
etherint = NSGigEInt(device=Parent.ethernet)
# ethernet = Sinic(configdata=SinicPciData(),
fs now gets to the point where it would really like a filesystem. Time to make the ide device work arch/alpha/system.cc: write the machine type and rev in the correct place cpu/simple/cpu.cc: reset the packet structure every time it's reused... wow the simple cpu code for talking to memory is getting horrible. dev/alpha_console.cc: move the setAlphaAccess to startup() to make sure that the console binary is loaded dev/tsunami_cchip.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: fix a couple of bugs injected in the newmem fixes mem/bus.cc: More verbose bus tracing mem/packet.hh: Add a constructor to packet to set the result to unknown and a reset method in the case it's being reused mem/vport.hh: don't need are own read/write methods since the base functional port ones call writeBlob readBlob which do the translation for us --HG-- extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 23:46:25 +02:00
# pci_bus=0, pci_dev=1, pci_func=0)
Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working after merge from head. Checkpointing may need some work now. Endian-happiness still not complete. SConscript: add all devices back into make file base/inet.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/pktfifo.cc: dev/pktfifo.hh: rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system configs/test/fs.py: add nics to fs.py cpu/cpu_exec_context.cc: remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the static virtual ports in the exec context cpu/simple/cpu.cc: cpu/simple/cpu.hh: dev/alpha_console.cc: dev/ide_ctrl.cc: use new methods for accessing packet data dev/ide_disk.cc: add some more dprintfs dev/io_device.cc: delete packets when we are done with them. Update for new packet methods to access data dev/isa_fake.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: dev/uart8250.hh: mem/physical.cc: mem/port.cc: dUpdate for new packet methods to access data dev/ns_gige.cc: Update for new memory system dev/ns_gige.hh: python/m5/objects/Ethernet.py: update for new memory system dev/sinic.cc: dev/sinic.hh: Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions mem/packet.hh: Add methods to access data instead of accessing it directly. --HG-- extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-25 01:31:50 +02:00
# etherint = SinicInt(device=Parent.ethernet)
fs now gets to the point where it would really like a filesystem. Time to make the ide device work arch/alpha/system.cc: write the machine type and rev in the correct place cpu/simple/cpu.cc: reset the packet structure every time it's reused... wow the simple cpu code for talking to memory is getting horrible. dev/alpha_console.cc: move the setAlphaAccess to startup() to make sure that the console binary is loaded dev/tsunami_cchip.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: fix a couple of bugs injected in the newmem fixes mem/bus.cc: More verbose bus tracing mem/packet.hh: Add a constructor to packet to set the result to unknown and a reset method in the case it's being reused mem/vport.hh: don't need are own read/write methods since the base functional port ones call writeBlob readBlob which do the translation for us --HG-- extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 23:46:25 +02:00
console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
# bridge = PciFake(configdata=BridgePciData(), pci_bus=0, pci_dev=2, pci_func=0)
#class FreeBSDTsunami(BaseTsunami):
# disk0 = FreeBSDRootDisk(delay='0us', driveID='master')
# ide = IdeController(disks=[Parent.disk0],
# configdata=IdeControllerPciData(),
# pci_func=0, pci_dev=0, pci_bus=0)
make ide disk work for newmem SConscript: compile ide devices base/chunk_generator.hh: add another parameter to the chuck generator called complete() which returns the number of bytes transfered so far. Very useful for adding to a pointer. configs/test/fs.py: Add ide disk to fs test configuration dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: update for new memory system mem/bus.cc: support devices that return multiple ranges remove old ranges before using new info mem/packet.hh: make senderstate void* per steve's request that we use every construct possible in C++ mem/physical.cc: have memory stamp the packet with the time. mem/physical.hh: actually set the memory latency variable python/m5/objects/Device.py: Add DmaDevice python/m5/objects/Ide.py: Ide disk no longer has a physmem pointer python/m5/objects/Pci.py: update pci device for newmem python/m5/objects/PhysicalMemory.py: add latency parameter for physical memory sim/byteswap.hh: use fast architecture dependent byteswap calls if they exist --HG-- extra : convert_revision : e3cf2e8f61064ad302d94bc22010a00c59f3f793
2006-04-20 23:14:30 +02:00
class LinuxTsunami(BaseTsunami):
disk0 = LinuxRootDisk(driveID='master')
disk1 = SpecwebFilesetDisk(driveID='slave')
disk2 = LinuxSwapDisk(driveID='master')
ide = IdeController(disks=[Parent.disk0, Parent.disk1, Parent.disk2],
configdata=IdeControllerPciData(),
pci_func=0, pci_dev=0, pci_bus=0)
fs now gets to the point where it would really like a filesystem. Time to make the ide device work arch/alpha/system.cc: write the machine type and rev in the correct place cpu/simple/cpu.cc: reset the packet structure every time it's reused... wow the simple cpu code for talking to memory is getting horrible. dev/alpha_console.cc: move the setAlphaAccess to startup() to make sure that the console binary is loaded dev/tsunami_cchip.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: fix a couple of bugs injected in the newmem fixes mem/bus.cc: More verbose bus tracing mem/packet.hh: Add a constructor to packet to set the result to unknown and a reset method in the case it's being reused mem/vport.hh: don't need are own read/write methods since the base functional port ones call writeBlob readBlob which do the translation for us --HG-- extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 23:46:25 +02:00
class LinuxAlphaSystem(LinuxAlphaSystem):
random mix of tidbits configs/test/fs.py: update fs.py to use a bus bridge cpu/simple/cpu.hh: cpu should just return that it doesn't snoop any address ranges python/m5/objects/System.py: move boot_osflags to system --HG-- extra : convert_revision : b4256df7eada7e65b69513361de8bffc3fdd680b
2006-04-28 21:40:45 +02:00
magicbus = Bus(bus_id=0)
magicbus2 = Bus(bus_id=1)
bridge = Bridge()
fs now gets to the point where it would really like a filesystem. Time to make the ide device work arch/alpha/system.cc: write the machine type and rev in the correct place cpu/simple/cpu.cc: reset the packet structure every time it's reused... wow the simple cpu code for talking to memory is getting horrible. dev/alpha_console.cc: move the setAlphaAccess to startup() to make sure that the console binary is loaded dev/tsunami_cchip.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: fix a couple of bugs injected in the newmem fixes mem/bus.cc: More verbose bus tracing mem/packet.hh: Add a constructor to packet to set the result to unknown and a reset method in the case it's being reused mem/vport.hh: don't need are own read/write methods since the base functional port ones call writeBlob readBlob which do the translation for us --HG-- extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 23:46:25 +02:00
physmem = PhysicalMemory(range = AddrRange('128MB'))
random mix of tidbits configs/test/fs.py: update fs.py to use a bus bridge cpu/simple/cpu.hh: cpu should just return that it doesn't snoop any address ranges python/m5/objects/System.py: move boot_osflags to system --HG-- extra : convert_revision : b4256df7eada7e65b69513361de8bffc3fdd680b
2006-04-28 21:40:45 +02:00
c0a = Connector(side_a=Parent.magicbus, side_b=Parent.bridge, side_b_name="side_a")
c0b = Connector(side_a=Parent.magicbus2, side_b=Parent.bridge, side_b_name="side_b")
c1 = Connector(side_a=Parent.physmem, side_b=Parent.magicbus2)
make ide disk work for newmem SConscript: compile ide devices base/chunk_generator.hh: add another parameter to the chuck generator called complete() which returns the number of bytes transfered so far. Very useful for adding to a pointer. configs/test/fs.py: Add ide disk to fs test configuration dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: update for new memory system mem/bus.cc: support devices that return multiple ranges remove old ranges before using new info mem/packet.hh: make senderstate void* per steve's request that we use every construct possible in C++ mem/physical.cc: have memory stamp the packet with the time. mem/physical.hh: actually set the memory latency variable python/m5/objects/Device.py: Add DmaDevice python/m5/objects/Ide.py: Ide disk no longer has a physmem pointer python/m5/objects/Pci.py: update pci device for newmem python/m5/objects/PhysicalMemory.py: add latency parameter for physical memory sim/byteswap.hh: use fast architecture dependent byteswap calls if they exist --HG-- extra : convert_revision : e3cf2e8f61064ad302d94bc22010a00c59f3f793
2006-04-20 23:14:30 +02:00
tsunami = LinuxTsunami()
fs now gets to the point where it would really like a filesystem. Time to make the ide device work arch/alpha/system.cc: write the machine type and rev in the correct place cpu/simple/cpu.cc: reset the packet structure every time it's reused... wow the simple cpu code for talking to memory is getting horrible. dev/alpha_console.cc: move the setAlphaAccess to startup() to make sure that the console binary is loaded dev/tsunami_cchip.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: fix a couple of bugs injected in the newmem fixes mem/bus.cc: More verbose bus tracing mem/packet.hh: Add a constructor to packet to set the result to unknown and a reset method in the case it's being reused mem/vport.hh: don't need are own read/write methods since the base functional port ones call writeBlob readBlob which do the translation for us --HG-- extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 23:46:25 +02:00
c2 = Connector(side_a=Parent.tsunami.cchip, side_a_name='pio', side_b=Parent.magicbus)
c3 = Connector(side_a=Parent.tsunami.pchip, side_a_name='pio', side_b=Parent.magicbus)
c4 = Connector(side_a=Parent.tsunami.pciconfig, side_a_name='pio', side_b=Parent.magicbus)
c5 = Connector(side_a=Parent.tsunami.fake_sm_chip, side_a_name='pio', side_b=Parent.magicbus)
Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working after merge from head. Checkpointing may need some work now. Endian-happiness still not complete. SConscript: add all devices back into make file base/inet.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/pktfifo.cc: dev/pktfifo.hh: rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system configs/test/fs.py: add nics to fs.py cpu/cpu_exec_context.cc: remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the static virtual ports in the exec context cpu/simple/cpu.cc: cpu/simple/cpu.hh: dev/alpha_console.cc: dev/ide_ctrl.cc: use new methods for accessing packet data dev/ide_disk.cc: add some more dprintfs dev/io_device.cc: delete packets when we are done with them. Update for new packet methods to access data dev/isa_fake.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: dev/uart8250.hh: mem/physical.cc: mem/port.cc: dUpdate for new packet methods to access data dev/ns_gige.cc: Update for new memory system dev/ns_gige.hh: python/m5/objects/Ethernet.py: update for new memory system dev/sinic.cc: dev/sinic.hh: Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions mem/packet.hh: Add methods to access data instead of accessing it directly. --HG-- extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-25 01:31:50 +02:00
c6 = Connector(side_a=Parent.tsunami.ethernet, side_a_name='pio', side_b=Parent.magicbus)
c6a = Connector(side_a=Parent.tsunami.ethernet, side_a_name='dma', side_b=Parent.magicbus)
fs now gets to the point where it would really like a filesystem. Time to make the ide device work arch/alpha/system.cc: write the machine type and rev in the correct place cpu/simple/cpu.cc: reset the packet structure every time it's reused... wow the simple cpu code for talking to memory is getting horrible. dev/alpha_console.cc: move the setAlphaAccess to startup() to make sure that the console binary is loaded dev/tsunami_cchip.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: fix a couple of bugs injected in the newmem fixes mem/bus.cc: More verbose bus tracing mem/packet.hh: Add a constructor to packet to set the result to unknown and a reset method in the case it's being reused mem/vport.hh: don't need are own read/write methods since the base functional port ones call writeBlob readBlob which do the translation for us --HG-- extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 23:46:25 +02:00
c7 = Connector(side_a=Parent.tsunami.fake_uart1, side_a_name='pio', side_b=Parent.magicbus)
c8 = Connector(side_a=Parent.tsunami.fake_uart2, side_a_name='pio', side_b=Parent.magicbus)
c9 = Connector(side_a=Parent.tsunami.fake_uart3, side_a_name='pio', side_b=Parent.magicbus)
c10 = Connector(side_a=Parent.tsunami.fake_uart4, side_a_name='pio', side_b=Parent.magicbus)
make ide disk work for newmem SConscript: compile ide devices base/chunk_generator.hh: add another parameter to the chuck generator called complete() which returns the number of bytes transfered so far. Very useful for adding to a pointer. configs/test/fs.py: Add ide disk to fs test configuration dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: update for new memory system mem/bus.cc: support devices that return multiple ranges remove old ranges before using new info mem/packet.hh: make senderstate void* per steve's request that we use every construct possible in C++ mem/physical.cc: have memory stamp the packet with the time. mem/physical.hh: actually set the memory latency variable python/m5/objects/Device.py: Add DmaDevice python/m5/objects/Ide.py: Ide disk no longer has a physmem pointer python/m5/objects/Pci.py: update pci device for newmem python/m5/objects/PhysicalMemory.py: add latency parameter for physical memory sim/byteswap.hh: use fast architecture dependent byteswap calls if they exist --HG-- extra : convert_revision : e3cf2e8f61064ad302d94bc22010a00c59f3f793
2006-04-20 23:14:30 +02:00
c11 = Connector(side_a=Parent.tsunami.ide, side_a_name='pio', side_b=Parent.magicbus)
c13 = Connector(side_a=Parent.tsunami.ide, side_a_name='dma', side_b=Parent.magicbus)
fs now gets to the point where it would really like a filesystem. Time to make the ide device work arch/alpha/system.cc: write the machine type and rev in the correct place cpu/simple/cpu.cc: reset the packet structure every time it's reused... wow the simple cpu code for talking to memory is getting horrible. dev/alpha_console.cc: move the setAlphaAccess to startup() to make sure that the console binary is loaded dev/tsunami_cchip.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: fix a couple of bugs injected in the newmem fixes mem/bus.cc: More verbose bus tracing mem/packet.hh: Add a constructor to packet to set the result to unknown and a reset method in the case it's being reused mem/vport.hh: don't need are own read/write methods since the base functional port ones call writeBlob readBlob which do the translation for us --HG-- extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 23:46:25 +02:00
c12 = Connector(side_a=Parent.tsunami.fake_ppc, side_a_name='pio', side_b=Parent.magicbus)
c14 = Connector(side_a=Parent.tsunami.fake_OROM, side_a_name='pio', side_b=Parent.magicbus)
c16 = Connector(side_a=Parent.tsunami.fake_pnp_addr, side_a_name='pio', side_b=Parent.magicbus)
c17 = Connector(side_a=Parent.tsunami.fake_pnp_write, side_a_name='pio', side_b=Parent.magicbus)
c18 = Connector(side_a=Parent.tsunami.fake_pnp_read0, side_a_name='pio', side_b=Parent.magicbus)
c19 = Connector(side_a=Parent.tsunami.fake_pnp_read1, side_a_name='pio', side_b=Parent.magicbus)
c20 = Connector(side_a=Parent.tsunami.fake_pnp_read2, side_a_name='pio', side_b=Parent.magicbus)
c21 = Connector(side_a=Parent.tsunami.fake_pnp_read3, side_a_name='pio', side_b=Parent.magicbus)
c22 = Connector(side_a=Parent.tsunami.fake_pnp_read4, side_a_name='pio', side_b=Parent.magicbus)
c23 = Connector(side_a=Parent.tsunami.fake_pnp_read5, side_a_name='pio', side_b=Parent.magicbus)
c24 = Connector(side_a=Parent.tsunami.fake_pnp_read6, side_a_name='pio', side_b=Parent.magicbus)
c25 = Connector(side_a=Parent.tsunami.fake_pnp_read7, side_a_name='pio', side_b=Parent.magicbus)
c27 = Connector(side_a=Parent.tsunami.fake_ata0, side_a_name='pio', side_b=Parent.magicbus)
c28 = Connector(side_a=Parent.tsunami.fake_ata1, side_a_name='pio', side_b=Parent.magicbus)
c30 = Connector(side_a=Parent.tsunami.fb, side_a_name='pio', side_b=Parent.magicbus)
c31 = Connector(side_a=Parent.tsunami.io, side_a_name='pio', side_b=Parent.magicbus)
c32 = Connector(side_a=Parent.tsunami.uart, side_a_name='pio', side_b=Parent.magicbus)
c33 = Connector(side_a=Parent.tsunami.console, side_a_name='pio', side_b=Parent.magicbus)
make ide disk work for newmem SConscript: compile ide devices base/chunk_generator.hh: add another parameter to the chuck generator called complete() which returns the number of bytes transfered so far. Very useful for adding to a pointer. configs/test/fs.py: Add ide disk to fs test configuration dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: update for new memory system mem/bus.cc: support devices that return multiple ranges remove old ranges before using new info mem/packet.hh: make senderstate void* per steve's request that we use every construct possible in C++ mem/physical.cc: have memory stamp the packet with the time. mem/physical.hh: actually set the memory latency variable python/m5/objects/Device.py: Add DmaDevice python/m5/objects/Ide.py: Ide disk no longer has a physmem pointer python/m5/objects/Pci.py: update pci device for newmem python/m5/objects/PhysicalMemory.py: add latency parameter for physical memory sim/byteswap.hh: use fast architecture dependent byteswap calls if they exist --HG-- extra : convert_revision : e3cf2e8f61064ad302d94bc22010a00c59f3f793
2006-04-20 23:14:30 +02:00
raw_image = RawDiskImage(image_file=disk('linux-latest.img'),
fs now gets to the point where it would really like a filesystem. Time to make the ide device work arch/alpha/system.cc: write the machine type and rev in the correct place cpu/simple/cpu.cc: reset the packet structure every time it's reused... wow the simple cpu code for talking to memory is getting horrible. dev/alpha_console.cc: move the setAlphaAccess to startup() to make sure that the console binary is loaded dev/tsunami_cchip.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: fix a couple of bugs injected in the newmem fixes mem/bus.cc: More verbose bus tracing mem/packet.hh: Add a constructor to packet to set the result to unknown and a reset method in the case it's being reused mem/vport.hh: don't need are own read/write methods since the base functional port ones call writeBlob readBlob which do the translation for us --HG-- extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 23:46:25 +02:00
read_only=True)
simple_disk = SimpleDisk(disk=Parent.raw_image)
intrctrl = IntrControl()
random mix of tidbits configs/test/fs.py: update fs.py to use a bus bridge cpu/simple/cpu.hh: cpu should just return that it doesn't snoop any address ranges python/m5/objects/System.py: move boot_osflags to system --HG-- extra : convert_revision : b4256df7eada7e65b69513361de8bffc3fdd680b
2006-04-28 21:40:45 +02:00
cpu = SimpleCPU(mem=Parent.magicbus2)
fs now gets to the point where it would really like a filesystem. Time to make the ide device work arch/alpha/system.cc: write the machine type and rev in the correct place cpu/simple/cpu.cc: reset the packet structure every time it's reused... wow the simple cpu code for talking to memory is getting horrible. dev/alpha_console.cc: move the setAlphaAccess to startup() to make sure that the console binary is loaded dev/tsunami_cchip.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: fix a couple of bugs injected in the newmem fixes mem/bus.cc: More verbose bus tracing mem/packet.hh: Add a constructor to packet to set the result to unknown and a reset method in the case it's being reused mem/vport.hh: don't need are own read/write methods since the base functional port ones call writeBlob readBlob which do the translation for us --HG-- extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 23:46:25 +02:00
sim_console = SimConsole(listener=ConsoleListener(port=3456))
Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working after merge from head. Checkpointing may need some work now. Endian-happiness still not complete. SConscript: add all devices back into make file base/inet.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/pktfifo.cc: dev/pktfifo.hh: rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system configs/test/fs.py: add nics to fs.py cpu/cpu_exec_context.cc: remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the static virtual ports in the exec context cpu/simple/cpu.cc: cpu/simple/cpu.hh: dev/alpha_console.cc: dev/ide_ctrl.cc: use new methods for accessing packet data dev/ide_disk.cc: add some more dprintfs dev/io_device.cc: delete packets when we are done with them. Update for new packet methods to access data dev/isa_fake.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: dev/uart8250.hh: mem/physical.cc: mem/port.cc: dUpdate for new packet methods to access data dev/ns_gige.cc: Update for new memory system dev/ns_gige.hh: python/m5/objects/Ethernet.py: update for new memory system dev/sinic.cc: dev/sinic.hh: Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions mem/packet.hh: Add methods to access data instead of accessing it directly. --HG-- extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-25 01:31:50 +02:00
kernel = '/z/saidi/work/m5.newmem/build/vmlinux'
fs now gets to the point where it would really like a filesystem. Time to make the ide device work arch/alpha/system.cc: write the machine type and rev in the correct place cpu/simple/cpu.cc: reset the packet structure every time it's reused... wow the simple cpu code for talking to memory is getting horrible. dev/alpha_console.cc: move the setAlphaAccess to startup() to make sure that the console binary is loaded dev/tsunami_cchip.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: fix a couple of bugs injected in the newmem fixes mem/bus.cc: More verbose bus tracing mem/packet.hh: Add a constructor to packet to set the result to unknown and a reset method in the case it's being reused mem/vport.hh: don't need are own read/write methods since the base functional port ones call writeBlob readBlob which do the translation for us --HG-- extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 23:46:25 +02:00
pal = binary('ts_osfpal')
console = binary('console')
boot_osflags = 'root=/dev/hda1 console=ttyS0'
Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working after merge from head. Checkpointing may need some work now. Endian-happiness still not complete. SConscript: add all devices back into make file base/inet.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/pktfifo.cc: dev/pktfifo.hh: rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system configs/test/fs.py: add nics to fs.py cpu/cpu_exec_context.cc: remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the static virtual ports in the exec context cpu/simple/cpu.cc: cpu/simple/cpu.hh: dev/alpha_console.cc: dev/ide_ctrl.cc: use new methods for accessing packet data dev/ide_disk.cc: add some more dprintfs dev/io_device.cc: delete packets when we are done with them. Update for new packet methods to access data dev/isa_fake.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: dev/uart8250.hh: mem/physical.cc: mem/port.cc: dUpdate for new packet methods to access data dev/ns_gige.cc: Update for new memory system dev/ns_gige.hh: python/m5/objects/Ethernet.py: update for new memory system dev/sinic.cc: dev/sinic.hh: Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions mem/packet.hh: Add methods to access data instead of accessing it directly. --HG-- extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-25 01:31:50 +02:00
# readfile = os.path.join(test_base, 'halt.sh')
fs now gets to the point where it would really like a filesystem. Time to make the ide device work arch/alpha/system.cc: write the machine type and rev in the correct place cpu/simple/cpu.cc: reset the packet structure every time it's reused... wow the simple cpu code for talking to memory is getting horrible. dev/alpha_console.cc: move the setAlphaAccess to startup() to make sure that the console binary is loaded dev/tsunami_cchip.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: fix a couple of bugs injected in the newmem fixes mem/bus.cc: More verbose bus tracing mem/packet.hh: Add a constructor to packet to set the result to unknown and a reset method in the case it's being reused mem/vport.hh: don't need are own read/write methods since the base functional port ones call writeBlob readBlob which do the translation for us --HG-- extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 23:46:25 +02:00
BaseCPU.itb = AlphaITB()
BaseCPU.dtb = AlphaDTB()
BaseCPU.system = Parent.any
Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working after merge from head. Checkpointing may need some work now. Endian-happiness still not complete. SConscript: add all devices back into make file base/inet.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/pktfifo.cc: dev/pktfifo.hh: rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system configs/test/fs.py: add nics to fs.py cpu/cpu_exec_context.cc: remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the static virtual ports in the exec context cpu/simple/cpu.cc: cpu/simple/cpu.hh: dev/alpha_console.cc: dev/ide_ctrl.cc: use new methods for accessing packet data dev/ide_disk.cc: add some more dprintfs dev/io_device.cc: delete packets when we are done with them. Update for new packet methods to access data dev/isa_fake.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: dev/uart8250.hh: mem/physical.cc: mem/port.cc: dUpdate for new packet methods to access data dev/ns_gige.cc: Update for new memory system dev/ns_gige.hh: python/m5/objects/Ethernet.py: update for new memory system dev/sinic.cc: dev/sinic.hh: Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions mem/packet.hh: Add methods to access data instead of accessing it directly. --HG-- extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-25 01:31:50 +02:00
class TsunamiRoot(System):
fs now gets to the point where it would really like a filesystem. Time to make the ide device work arch/alpha/system.cc: write the machine type and rev in the correct place cpu/simple/cpu.cc: reset the packet structure every time it's reused... wow the simple cpu code for talking to memory is getting horrible. dev/alpha_console.cc: move the setAlphaAccess to startup() to make sure that the console binary is loaded dev/tsunami_cchip.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: fix a couple of bugs injected in the newmem fixes mem/bus.cc: More verbose bus tracing mem/packet.hh: Add a constructor to packet to set the result to unknown and a reset method in the case it's being reused mem/vport.hh: don't need are own read/write methods since the base functional port ones call writeBlob readBlob which do the translation for us --HG-- extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 23:46:25 +02:00
pass
Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working after merge from head. Checkpointing may need some work now. Endian-happiness still not complete. SConscript: add all devices back into make file base/inet.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/pktfifo.cc: dev/pktfifo.hh: rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system configs/test/fs.py: add nics to fs.py cpu/cpu_exec_context.cc: remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the static virtual ports in the exec context cpu/simple/cpu.cc: cpu/simple/cpu.hh: dev/alpha_console.cc: dev/ide_ctrl.cc: use new methods for accessing packet data dev/ide_disk.cc: add some more dprintfs dev/io_device.cc: delete packets when we are done with them. Update for new packet methods to access data dev/isa_fake.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: dev/uart8250.hh: mem/physical.cc: mem/port.cc: dUpdate for new packet methods to access data dev/ns_gige.cc: Update for new memory system dev/ns_gige.hh: python/m5/objects/Ethernet.py: update for new memory system dev/sinic.cc: dev/sinic.hh: Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions mem/packet.hh: Add methods to access data instead of accessing it directly. --HG-- extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e
2006-04-25 01:31:50 +02:00
def DualRoot(ClientSystem, ServerSystem):
self = Root()
self.client = ClientSystem()
self.server = ServerSystem()
self.etherdump = EtherDump(file='ethertrace')
self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
int2 = Parent.server.tsunami.etherint[0],
dump = Parent.etherdump)
self.clock = '5GHz'
return self
root = DualRoot(ClientSystem = LinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')),
ServerSystem = LinuxAlphaSystem(readfile=script('netperf-server.rcS')))
Reference in a new issue Copy permalink