2006-09-19 02:12:45 +02:00
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/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/* @file
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* Device model for Intel's 8254x line of gigabit ethernet controllers.
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2006-10-20 19:00:05 +02:00
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* In particular an 82547 revision 2 (82547GI) MAC because it seems to have the
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* fewest workarounds in the driver. It will probably work with most of the
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* other MACs with slight modifications.
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2006-09-19 02:12:45 +02:00
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*/
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#include "base/inet.hh"
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#include "dev/i8254xGBe.hh"
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#include "mem/packet.hh"
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2006-10-27 15:10:50 +02:00
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#include "mem/packet_access.hh"
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2006-09-19 02:12:45 +02:00
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#include "sim/builder.hh"
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#include "sim/stats.hh"
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#include "sim/system.hh"
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2006-10-20 19:00:05 +02:00
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using namespace iGbReg;
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2006-09-19 02:12:45 +02:00
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IGbE::IGbE(Params *p)
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: PciDev(p), etherInt(NULL)
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{
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2006-10-20 19:00:05 +02:00
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// Initialized internal registers per Intel documentation
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regs.tctl.reg = 0;
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regs.rctl.reg = 0;
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regs.ctrl.reg = 0;
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regs.ctrl.fd = 1;
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regs.ctrl.lrst = 1;
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regs.ctrl.speed = 2;
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regs.ctrl.frcspd = 1;
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regs.sts.reg = 0;
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regs.eecd.reg = 0;
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regs.eecd.fwe = 1;
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regs.eecd.ee_type = 1;
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regs.eerd.reg = 0;
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regs.icd.reg = 0;
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regs.imc.reg = 0;
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regs.rctl.reg = 0;
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regs.tctl.reg = 0;
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regs.manc.reg = 0;
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2006-10-27 15:10:50 +02:00
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regs.pba.rxa = 0x30;
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regs.pba.txa = 0x10;
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2006-10-20 19:00:05 +02:00
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eeOpBits = 0;
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eeAddrBits = 0;
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eeDataBits = 0;
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eeOpcode = 0;
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2006-09-19 02:12:45 +02:00
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2006-10-27 15:10:50 +02:00
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// clear all 64 16 bit words of the eeprom
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memset(&flash, 0, EEPROM_SIZE*2);
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2006-10-20 19:00:05 +02:00
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// Magic happy checksum value
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flash[0] = 0xBABA;
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2006-09-19 02:12:45 +02:00
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}
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Tick
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2006-10-20 09:10:12 +02:00
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IGbE::writeConfig(PacketPtr pkt)
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2006-09-19 02:12:45 +02:00
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{
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int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
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if (offset < PCI_DEVICE_SPECIFIC)
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PciDev::writeConfig(pkt);
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else
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panic("Device specific PCI config space not implemented.\n");
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///
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/// Some work may need to be done here based for the pci COMMAND bits.
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///
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return pioDelay;
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}
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Tick
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2006-10-20 09:10:12 +02:00
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IGbE::read(PacketPtr pkt)
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2006-09-19 02:12:45 +02:00
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{
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int bar;
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Addr daddr;
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if (!getBAR(pkt->getAddr(), bar, daddr))
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panic("Invalid PCI memory access to unmapped memory.\n");
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// Only Memory register BAR is allowed
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assert(bar == 0);
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2006-10-20 19:00:05 +02:00
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// Only 32bit accesses allowed
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assert(pkt->getSize() == 4);
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2006-09-19 02:12:45 +02:00
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2006-10-27 15:10:50 +02:00
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//DPRINTF(Ethernet, "Read device register %#X\n", daddr);
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2006-09-19 02:12:45 +02:00
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2006-10-20 19:00:05 +02:00
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pkt->allocate();
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2006-09-19 02:12:45 +02:00
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///
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/// Handle read of register here
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///
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2006-10-27 15:10:50 +02:00
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2006-10-20 19:00:05 +02:00
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switch (daddr) {
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case CTRL:
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pkt->set<uint32_t>(regs.ctrl.reg);
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break;
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case STATUS:
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pkt->set<uint32_t>(regs.sts.reg);
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break;
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case EECD:
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pkt->set<uint32_t>(regs.eecd.reg);
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break;
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case EERD:
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pkt->set<uint32_t>(regs.eerd.reg);
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break;
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case ICR:
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pkt->set<uint32_t>(regs.icd.reg);
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break;
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case IMC:
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pkt->set<uint32_t>(regs.imc.reg);
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break;
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case RCTL:
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pkt->set<uint32_t>(regs.rctl.reg);
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break;
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case TCTL:
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pkt->set<uint32_t>(regs.tctl.reg);
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break;
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2006-10-27 15:10:50 +02:00
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case PBA:
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pkt->set<uint32_t>(regs.pba.reg);
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break;
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case WUC:
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case LEDCTL:
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pkt->set<uint32_t>(0); // We don't care, so just return 0
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break;
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2006-10-20 19:00:05 +02:00
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case MANC:
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pkt->set<uint32_t>(regs.manc.reg);
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break;
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default:
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2006-10-27 15:10:50 +02:00
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if (!(daddr >= VFTA && daddr < (VFTA + VLAN_FILTER_TABLE_SIZE)*4) &&
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!(daddr >= RAL && daddr < (RAL + RCV_ADDRESS_TABLE_SIZE)*4) &&
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!(daddr >= MTA && daddr < (MTA + MULTICAST_TABLE_SIZE)*4))
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pkt->set<uint32_t>(0);
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else
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panic("Read request to unknown register number: %#x\n", daddr);
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2006-10-20 19:00:05 +02:00
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};
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2006-09-19 02:12:45 +02:00
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pkt->result = Packet::Success;
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return pioDelay;
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}
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Tick
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2006-10-20 09:10:12 +02:00
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IGbE::write(PacketPtr pkt)
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2006-09-19 02:12:45 +02:00
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{
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int bar;
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Addr daddr;
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2006-10-20 19:00:05 +02:00
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2006-09-19 02:12:45 +02:00
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if (!getBAR(pkt->getAddr(), bar, daddr))
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panic("Invalid PCI memory access to unmapped memory.\n");
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// Only Memory register BAR is allowed
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assert(bar == 0);
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2006-10-20 19:00:05 +02:00
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// Only 32bit accesses allowed
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assert(pkt->getSize() == sizeof(uint32_t));
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2006-10-27 15:10:50 +02:00
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//DPRINTF(Ethernet, "Wrote device register %#X value %#X\n", daddr, pkt->get<uint32_t>());
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2006-09-19 02:12:45 +02:00
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///
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/// Handle write of register here
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///
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2006-10-20 19:00:05 +02:00
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uint32_t val = pkt->get<uint32_t>();
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switch (daddr) {
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case CTRL:
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regs.ctrl.reg = val;
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break;
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case STATUS:
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regs.sts.reg = val;
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break;
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case EECD:
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int oldClk;
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oldClk = regs.eecd.sk;
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regs.eecd.reg = val;
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// See if this is a eeprom access and emulate accordingly
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if (!oldClk && regs.eecd.sk) {
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if (eeOpBits < 8) {
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eeOpcode = eeOpcode << 1 | regs.eecd.din;
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eeOpBits++;
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} else if (eeAddrBits < 8 && eeOpcode == EEPROM_READ_OPCODE_SPI) {
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eeAddr = eeAddr << 1 | regs.eecd.din;
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eeAddrBits++;
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} else if (eeDataBits < 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) {
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2006-10-27 15:10:50 +02:00
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assert(eeAddr>>1 < EEPROM_SIZE);
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DPRINTF(EthernetEEPROM, "EEPROM bit read: %d word: %#X\n",
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flash[eeAddr>>1] >> eeDataBits & 0x1, flash[eeAddr>>1]);
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regs.eecd.dout = (flash[eeAddr>>1] >> (15-eeDataBits)) & 0x1;
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2006-10-20 19:00:05 +02:00
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eeDataBits++;
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} else if (eeDataBits < 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI) {
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regs.eecd.dout = 0;
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eeDataBits++;
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} else
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panic("What's going on with eeprom interface? opcode:"
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" %#x:%d addr: %#x:%d, data: %d\n", (uint32_t)eeOpcode,
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(uint32_t)eeOpBits, (uint32_t)eeAddr,
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(uint32_t)eeAddrBits, (uint32_t)eeDataBits);
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// Reset everything for the next command
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if ((eeDataBits == 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) ||
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(eeDataBits == 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI)) {
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eeOpBits = 0;
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eeAddrBits = 0;
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eeDataBits = 0;
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eeOpcode = 0;
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eeAddr = 0;
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}
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2006-10-27 15:10:50 +02:00
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DPRINTF(EthernetEEPROM, "EEPROM: opcode: %#X:%d addr: %#X:%d\n",
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(uint32_t)eeOpcode, (uint32_t) eeOpBits,
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(uint32_t)eeAddr>>1, (uint32_t)eeAddrBits);
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2006-10-20 19:00:05 +02:00
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if (eeOpBits == 8 && !(eeOpcode == EEPROM_READ_OPCODE_SPI ||
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eeOpcode == EEPROM_RDSR_OPCODE_SPI ))
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panic("Unknown eeprom opcode: %#X:%d\n", (uint32_t)eeOpcode,
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(uint32_t)eeOpBits);
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}
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// If driver requests eeprom access, immediately give it to it
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regs.eecd.ee_gnt = regs.eecd.ee_req;
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break;
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case EERD:
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regs.eerd.reg = val;
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break;
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case ICR:
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regs.icd.reg = val;
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break;
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case IMC:
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regs.imc.reg = val;
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break;
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case RCTL:
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regs.rctl.reg = val;
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break;
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case TCTL:
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regs.tctl.reg = val;
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break;
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2006-10-27 15:10:50 +02:00
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case PBA:
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regs.pba.rxa = val;
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regs.pba.txa = 64 - regs.pba.rxa;
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break;
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case WUC:
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case LEDCTL:
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; // We don't care, so don't store anything
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break;
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2006-10-20 19:00:05 +02:00
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case MANC:
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regs.manc.reg = val;
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break;
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default:
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2006-10-27 15:10:50 +02:00
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if (!(daddr >= VFTA && daddr < (VFTA + VLAN_FILTER_TABLE_SIZE)*4) &&
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!(daddr >= RAL && daddr < (RAL + RCV_ADDRESS_TABLE_SIZE)*4) &&
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!(daddr >= MTA && daddr < (MTA + MULTICAST_TABLE_SIZE)*4))
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panic("Write request to unknown register number: %#x\n", daddr);
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2006-10-20 19:00:05 +02:00
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};
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2006-09-19 02:12:45 +02:00
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pkt->result = Packet::Success;
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return pioDelay;
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}
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bool
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IGbE::ethRxPkt(EthPacketPtr packet)
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{
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panic("Need to implemenet\n");
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}
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void
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IGbE::ethTxDone()
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{
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panic("Need to implemenet\n");
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}
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void
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IGbE::serialize(std::ostream &os)
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{
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panic("Need to implemenet\n");
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}
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void
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IGbE::unserialize(Checkpoint *cp, const std::string §ion)
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{
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panic("Need to implemenet\n");
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
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SimObjectParam<EtherInt *> peer;
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SimObjectParam<IGbE *> device;
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END_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
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BEGIN_INIT_SIM_OBJECT_PARAMS(IGbEInt)
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INIT_PARAM_DFLT(peer, "peer interface", NULL),
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INIT_PARAM(device, "Ethernet device of this interface")
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END_INIT_SIM_OBJECT_PARAMS(IGbEInt)
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CREATE_SIM_OBJECT(IGbEInt)
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{
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IGbEInt *dev_int = new IGbEInt(getInstanceName(), device);
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EtherInt *p = (EtherInt *)peer;
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if (p) {
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dev_int->setPeer(p);
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p->setPeer(dev_int);
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}
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|
|
|
return dev_int;
|
|
|
|
}
|
|
|
|
|
|
|
|
REGISTER_SIM_OBJECT("IGbEInt", IGbEInt)
|
|
|
|
|
|
|
|
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbE)
|
|
|
|
|
|
|
|
SimObjectParam<System *> system;
|
|
|
|
SimObjectParam<Platform *> platform;
|
|
|
|
SimObjectParam<PciConfigData *> configdata;
|
|
|
|
Param<uint32_t> pci_bus;
|
|
|
|
Param<uint32_t> pci_dev;
|
|
|
|
Param<uint32_t> pci_func;
|
|
|
|
Param<Tick> pio_latency;
|
|
|
|
Param<Tick> config_latency;
|
|
|
|
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(IGbE)
|
|
|
|
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(IGbE)
|
|
|
|
|
|
|
|
INIT_PARAM(system, "System pointer"),
|
|
|
|
INIT_PARAM(platform, "Platform pointer"),
|
|
|
|
INIT_PARAM(configdata, "PCI Config data"),
|
|
|
|
INIT_PARAM(pci_bus, "PCI bus ID"),
|
|
|
|
INIT_PARAM(pci_dev, "PCI device number"),
|
|
|
|
INIT_PARAM(pci_func, "PCI function code"),
|
|
|
|
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
|
|
|
|
INIT_PARAM(config_latency, "Number of cycles for a config read or write")
|
|
|
|
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(IGbE)
|
|
|
|
|
|
|
|
|
|
|
|
CREATE_SIM_OBJECT(IGbE)
|
|
|
|
{
|
|
|
|
IGbE::Params *params = new IGbE::Params;
|
|
|
|
|
|
|
|
params->name = getInstanceName();
|
|
|
|
params->platform = platform;
|
|
|
|
params->system = system;
|
|
|
|
params->configData = configdata;
|
|
|
|
params->busNum = pci_bus;
|
|
|
|
params->deviceNum = pci_dev;
|
|
|
|
params->functionNum = pci_func;
|
|
|
|
params->pio_delay = pio_latency;
|
|
|
|
params->config_delay = config_latency;
|
|
|
|
|
|
|
|
return new IGbE(params);
|
|
|
|
}
|
|
|
|
|
|
|
|
REGISTER_SIM_OBJECT("IGbE", IGbE)
|