2011-04-25 23:18:08 +02:00
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---------- Begin Simulation Statistics ----------
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2011-09-13 18:58:09 +02:00
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sim_seconds 0.493848 # Number of seconds simulated
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sim_ticks 493847859500 # Number of ticks simulated
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2011-04-25 23:18:08 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-09-13 18:58:09 +02:00
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host_inst_rate 141014 # Simulator instruction rate (inst/s)
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host_tick_rate 45545926 # Simulator tick rate (ticks/s)
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host_mem_usage 250808 # Number of bytes of host memory used
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host_seconds 10842.85 # Real time elapsed on the host
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2011-04-25 23:18:08 +02:00
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sim_insts 1528988756 # Number of instructions simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.workload.num_syscalls 551 # Number of system calls
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2011-09-13 18:58:09 +02:00
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system.cpu.numCycles 987695720 # number of cpu cycles simulated
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2011-05-23 17:59:13 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-09-13 18:58:09 +02:00
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system.cpu.BPredUnit.lookups 245701836 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 245701836 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 16595687 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 236380847 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 218346080 # Number of BTB hits
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2011-04-25 23:18:08 +02:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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2011-05-23 17:59:13 +02:00
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.icacheStallCycles 205619767 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 1343825400 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 245701836 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 218346080 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 436746169 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 120030037 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 218211728 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 32810 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 394519 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 194794908 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 4074174 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 964173518 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.600326 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.317708 # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::0 531478687 55.12% 55.12% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 32400706 3.36% 58.48% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 38829894 4.03% 62.51% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 32544605 3.38% 65.89% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 21858974 2.27% 68.15% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 36433886 3.78% 71.93% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 49094534 5.09% 77.02% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 36959436 3.83% 80.86% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 184572796 19.14% 100.00% # Number of instructions fetched each cycle (Total)
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2011-05-23 17:59:13 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::total 964173518 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.248763 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.360566 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 264598468 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 174292947 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 373121057 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 48992521 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 103168525 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 2446276906 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 103168525 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 301836329 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 39995204 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 12425 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 383530410 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 135630625 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 2393744264 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 2638 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 25354791 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 92046607 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 28 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 2227310497 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 5630161832 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 5629928430 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 233402 # Number of floating rename lookups
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2011-05-23 17:59:13 +02:00
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system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
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2011-09-13 18:58:09 +02:00
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system.cpu.rename.UndoneMaps 800011470 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 1318 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 1303 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 319166295 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 577919050 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 226606684 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 227271329 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 66051723 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 2286915029 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 6159 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 1922683409 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 1316831 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 755416366 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 1189575311 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 5606 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 964173518 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.994126 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.811461 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::0 282941420 29.35% 29.35% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 159777972 16.57% 45.92% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 162985907 16.90% 62.82% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 148632114 15.42% 78.24% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 109327758 11.34% 89.58% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 60035944 6.23% 95.80% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 30803018 3.19% 99.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 8626659 0.89% 99.89% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 1042726 0.11% 100.00% # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::total 964173518 # Number of insts issued each cycle
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.fu_full::IntAlu 2258663 14.74% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 9960479 65.00% 79.74% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 3103804 20.26% 100.00% # attempts to use FU when none available
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.FU_type_0::No_OpClass 2419995 0.13% 0.13% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 1274972987 66.31% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 9 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 463702844 24.12% 90.56% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 181587574 9.44% 100.00% # Type of FU issued
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2011-05-23 17:59:13 +02:00
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.FU_type_0::total 1922683409 # Type of FU issued
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system.cpu.iq.rate 1.946635 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 15322946 # FU busy when requested
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|
|
system.cpu.iq.fu_busy_rate 0.007970 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 4826174769 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 3042532180 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1874952899 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 5344 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 78632 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 143 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 1935584605 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 1755 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 158265730 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 193816890 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 368616 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 283851 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 77446847 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2334 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 103168525 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 9000117 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1434115 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 2286921188 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 1114031 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 577919050 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 226607032 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 6159 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 1032728 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 29962 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 283851 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 15679501 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 2385329 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 18064830 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 1889474492 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 454765570 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 33208917 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.exec_refs 629342688 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 176743901 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 174577118 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.913013 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 1882825411 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 1874953042 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1440779649 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 2134933130 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.wb_rate 1.898310 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.674859 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 757942908 # The number of squashed insts skipped by commit
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.branchMispredicts 16623561 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 861004993 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.775819 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.288206 # Number of insts commited each cycle
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 338275347 39.29% 39.29% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 210593488 24.46% 63.75% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 75171542 8.73% 72.48% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 92637359 10.76% 83.24% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 34049472 3.95% 87.19% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 27973994 3.25% 90.44% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 16051033 1.86% 92.31% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 12256013 1.42% 93.73% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 53996745 6.27% 100.00% # Number of insts commited each cycle
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 861004993 # Number of insts commited each cycle
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.count 1528988756 # Number of instructions committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 533262345 # Number of memory references committed
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.commit.loads 384102160 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.branches 149758588 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 53996745 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.rob.rob_reads 3093939912 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 4677211584 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 604649 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 23522202 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.cpi 0.645980 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.645980 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.548036 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.548036 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 3179615221 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 1745014633 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 160 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 9 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 1039384818 # number of misc regfile reads
|
|
|
|
|
system.cpu.icache.replacements 9994 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 979.138170 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 194574782 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 11491 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 16932.798016 # Average number of references to valid blocks.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 979.138170 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.478095 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 194581368 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 194581368 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 194581368 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 213540 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 213540 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 213540 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 1483328000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 1483328000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 1483328000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 194794908 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 194794908 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 194794908 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.001096 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.001096 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.001096 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 6946.370703 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 6946.370703 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 6946.370703 # average overall miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.writebacks 7 # number of writebacks
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 2095 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 2095 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 2095 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 211445 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 211445 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 211445 # number of overall MSHR misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 798407000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 798407000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 798407000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.001085 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.001085 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.001085 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3775.955922 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 3775.955922 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 3775.955922 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.replacements 2527816 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4087.589623 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 440722661 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 2531912 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 174.067132 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 2123837000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 4087.589623 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.997947 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 291994352 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 147612028 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits 439606380 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 439606380 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 3097887 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 1548173 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 4646060 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 4646060 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 51505231500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 36276487000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 87781718500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 87781718500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 295092239 # number of ReadReq accesses(hits+misses)
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_accesses 444252440 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 444252440 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.010498 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.010379 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.010458 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.010458 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 16625.923250 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 23431.804456 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 18893.797863 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 18893.797863 # average overall miss latency
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.writebacks 2229445 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 1337511 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 584931 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 1922442 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 1922442 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 1760376 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 963242 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 2723618 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 2723618 # number of overall MSHR misses
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 14910828500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 16810626500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 31721455000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 31721455000 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005966 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006458 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.006131 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.006131 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8470.252094 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17452.131967 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 11646.807665 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 11646.807665 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.replacements 574929 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 21600.538558 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 3193840 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 594089 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 5.376030 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 271573746000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 7800.784816 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 13799.753742 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.238061 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.421135 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 1433037 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 2229452 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits 1223 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 524485 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 1957522 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 1957522 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 338639 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 198705 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 247104 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 585743 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 585743 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 11565729500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 9755500 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 8475498500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 20041228000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 20041228000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 1771676 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 2229452 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 199928 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 771589 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 2543265 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 2543265 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.191140 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.993883 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.320253 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.230311 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.230311 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34153.566187 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 49.095393 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34299.317292 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34215.053360 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34215.053360 # average overall miss latency
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.writebacks 411255 # number of writebacks
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 338639 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 198705 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 247104 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 585743 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 585743 # number of overall MSHR misses
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 10504876500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6160011500 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7664207000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 18169083500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 18169083500 # number of overall MSHR miss cycles
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191140 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.993883 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320253 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.230311 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.230311 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.870307 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.787600 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31016.118719 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.865782 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.865782 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2011-04-25 23:18:08 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-04-25 23:18:08 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
