2015-02-16 09:32:38 +01:00
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/*
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* Copyright (c) 2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#include "cpu/inst_pb_trace.hh"
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#include "base/callback.hh"
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#include "base/output.hh"
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#include "config/the_isa.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "debug/ExecEnable.hh"
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#include "params/InstPBTrace.hh"
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#include "proto/inst.pb.h"
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#include "sim/core.hh"
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namespace Trace {
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ProtoOutputStream *InstPBTrace::traceStream;
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void
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InstPBTraceRecord::dump()
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{
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// We're trying to build an instruction trace so we just want macro-ops and
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// instructions that aren't macro-oped
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if ((macroStaticInst && staticInst->isFirstMicroop()) ||
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!staticInst->isMicroop()) {
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tracer.traceInst(thread, staticInst, pc);
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}
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// If this instruction accessed memory lets record it
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if (getMemValid())
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tracer.traceMem(staticInst, getAddr(), getSize(), getFlags());
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}
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InstPBTrace::InstPBTrace(const InstPBTraceParams *p)
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: InstTracer(p), curMsg(nullptr)
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{
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// Create our output file
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createTraceFile(p->file_name);
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}
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void
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InstPBTrace::createTraceFile(std::string filename)
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{
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// Since there is only one output file for all tracers check if it exists
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if (traceStream)
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return;
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traceStream = new ProtoOutputStream(simout.resolve(filename));
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// Output the header
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ProtoMessage::InstHeader header_msg;
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header_msg.set_obj_id("gem5 generated instruction trace");
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header_msg.set_ver(0);
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header_msg.set_tick_freq(SimClock::Frequency);
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header_msg.set_has_mem(true);
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traceStream->write(header_msg);
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// get a callback when we exit so we can close the file
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Callback *cb = new MakeCallback<InstPBTrace,
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&InstPBTrace::closeStreams>(this);
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registerExitCallback(cb);
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}
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void
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InstPBTrace::closeStreams()
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{
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if (curMsg) {
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traceStream->write(*curMsg);
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delete curMsg;
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curMsg = NULL;
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}
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if (!traceStream)
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return;
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delete traceStream;
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traceStream = NULL;
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}
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InstPBTrace::~InstPBTrace()
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{
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closeStreams();
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}
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InstPBTraceRecord*
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InstPBTrace::getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr si,
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TheISA::PCState pc, const StaticInstPtr mi)
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{
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2015-09-30 22:21:55 +02:00
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// Only record the trace if Exec debugging is enabled
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if (!Debug::ExecEnable)
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2015-02-16 09:32:38 +01:00
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return NULL;
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return new InstPBTraceRecord(*this, when, tc, si, pc, mi);
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}
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void
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InstPBTrace::traceInst(ThreadContext *tc, StaticInstPtr si, TheISA::PCState pc)
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{
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if (curMsg) {
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/// @todo if we are running multi-threaded I assume we'd need a lock here
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traceStream->write(*curMsg);
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delete curMsg;
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curMsg = NULL;
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}
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// Create a new instruction message and fill out the fields
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curMsg = new ProtoMessage::Inst;
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curMsg->set_pc(pc.pc());
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curMsg->set_inst(static_cast<uint32_t>(bits(si->machInst, 31, 0)));
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curMsg->set_cpuid(tc->cpuId());
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curMsg->set_tick(curTick());
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curMsg->set_type(static_cast<ProtoMessage::Inst_InstType>(si->opClass()));
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curMsg->set_inst_flags(bits(si->machInst, 7, 0));
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}
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void
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InstPBTrace::traceMem(StaticInstPtr si, Addr a, Addr s, unsigned f)
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{
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panic_if(!curMsg, "Memory access w/o msg?!");
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// We do a poor job identifying macro-ops that are load/stores
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curMsg->set_type(static_cast<ProtoMessage::Inst_InstType>(si->opClass()));
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ProtoMessage::Inst::MemAccess *mem_msg = curMsg->add_mem_access();
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mem_msg->set_addr(a);
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mem_msg->set_size(s);
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mem_msg->set_mem_flags(f);
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}
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} // namespace Trace
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Trace::InstPBTrace*
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InstPBTraceParams::create()
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{
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return new Trace::InstPBTrace(this);
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}
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