gem5/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout

gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Sep 21 2012 11:19:00
gem5 started Sep 21 2012 11:19:07
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0.  Starting simulation...
Hello world!
Exiting @ tick 27316000 because target called exit()
stats: Update stats for final tick and memory bandwidth patches 2012-01-25 18:19:50 +01:00			`gem5 Simulator System. http://gem5.org`
			`gem5 is copyrighted software; use the --copyright option for details.`
ARM/O3: Add regressions for ARM w/ O3 CPU. 2011-01-18 23:30:06 +01:00
ARM: update stats for bp and squash fixes. 2012-09-25 18:49:41 +02:00			`gem5 compiled Sep 21 2012 11:19:00`
			`gem5 started Sep 21 2012 11:19:07`
			`gem5 executing on u200540-lin`
			`command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing`
ARM/O3: Add regressions for ARM w/ O3 CPU. 2011-01-18 23:30:06 +01:00			`Global frequency set at 1000000000000 ticks per second`
			`info: Entering event queue @ 0. Starting simulation...`
			`Hello world!`
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes. 2012-07-09 18:35:41 +02:00			`Exiting @ tick 27316000 because target called exit()`