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gem5/src/cpu/legiontrace.cc

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Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
/*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
* Lisa Hsu
* Nathan Binkert
* Steve Raasch
*/
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
2009-09-23 17:34:21 +02:00
#include "config/the_isa.hh"
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
#if THE_ISA != SPARC_ISA
#error Legion tracing only works with SPARC simulations!
#endif
#include "config/full_system.hh"
#if !FULL_SYSTEM
#error Legion tracing only works in full system!
#endif
#include <sys/ipc.h>
#include <sys/shm.h>
build: fix compile problems pointed out by gcc 4.4
2009-11-05 01:57:01 +01:00
#include <cstdio>
#include <iomanip>
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
#include "arch/sparc/predecoder.hh"
Registers: Add a registers.hh file as an ISA switched header. This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. --HG-- rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
2009-07-09 08:02:21 +02:00
#include "arch/sparc/registers.hh"
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
#include "arch/sparc/utility.hh"
#include "base/socket.hh"
#include "cpu/base.hh"
Decode: Pull instruction decoding out of the StaticInst class into its own. This change pulls the instruction decoding machinery (including caches) out of the StaticInst class and puts it into its own class. This has a few intrinsic benefits. First, the StaticInst code, which has gotten to be quite large, gets simpler. Second, the code that handles decode caching is now separated out into its own component and can be looked at in isolation, making it easier to understand. I took the opportunity to restructure the code a bit which will hopefully also help. Beyond that, this change also lays some ground work for each ISA to have its own, potentially stateful decode object. We'd be able to include less contextualizing information in the ExtMachInst objects since that context would be applied at the decoder. Also, the decoder could "know" ahead of time that all the instructions it's going to see are going to be, for instance, 64 bit mode, and it will have one less thing to check when it decodes them. Because the decode caching mechanism has been separated out, it's now possible to have multiple caches which correspond to different types of decoding context. Having one cache for each element of the cross product of different configurations may become prohibitive, so it may be desirable to clear out the cache when relatively static state changes and not to have one for each setting. Because the decode function is no longer universally accessible as a static member of the StaticInst class, a new function was added to the ThreadContexts that returns the applicable decode object.
2011-09-09 11:30:01 +02:00
#include "cpu/decode.hh"
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
#include "cpu/legiontrace.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/system.hh"
#if FULL_SYSTEM
#include "arch/tlb.hh"
#endif
//XXX This is temporary
#include "cpu/m5legion_interface.h"
using namespace std;
using namespace TheISA;
#if FULL_SYSTEM
static int diffcount = 0;
static bool wasMicro = false;
#endif
namespace Trace {
SharedData *shared_data = NULL;
void
setupSharedData()
{
int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
if (shmfd < 0)
fatal("Couldn't get shared memory fd. Is Legion running?");
shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
if (shared_data == (SharedData*)-1)
fatal("Couldn't allocate shared memory");
if (shared_data->flags != OWN_M5)
fatal("Shared memory has invalid owner");
if (shared_data->version != VERSION)
fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
shared_data->version);
// step legion forward one cycle so we can get register values
shared_data->flags = OWN_LEGION;
}
////////////////////////////////////////////////////////////////////////
//
// Utility methods for pretty printing a report about a difference
//
String constant const-ness changes to placate g++ 4.2. Also some bug fixes in MIPS ISA uncovered by g++ warnings (Python string compares don't work in C++!). --HG-- extra : convert_revision : b347cc0108f23890e9b73b3ee96059f0cea96cf6
2007-11-01 02:04:22 +01:00
inline char * genCenteredLabel(int length, char * buffer, const char * label)
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
{
int labelLength = strlen(label);
assert(labelLength <= length);
int leftPad = (length - labelLength) / 2;
int rightPad = length - leftPad - labelLength;
char format[64];
sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad);
sprintf(buffer, format, "", label, "");
return buffer;
}
inline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b)
{
ccprintf(os, " %16s | %#018x %s %#-018x \n",
title, a, (a == b) ? "|" : "X", b);
}
inline void printColumnLabels(ostream & os)
{
static char * regLabel = genCenteredLabel(16, new char[17], "Register");
static char * m5Label = genCenteredLabel(18, new char[18], "M5");
static char * legionLabel = genCenteredLabel(18, new char[18], "Legion");
ccprintf(os, " %s | %s | %s \n", regLabel, m5Label, legionLabel);
ccprintf(os, "--------------------+-----------------------+-----------------------\n");
}
String constant const-ness changes to placate g++ 4.2. Also some bug fixes in MIPS ISA uncovered by g++ warnings (Python string compares don't work in C++!). --HG-- extra : convert_revision : b347cc0108f23890e9b73b3ee96059f0cea96cf6
2007-11-01 02:04:22 +01:00
inline void printSectionHeader(ostream & os, const char * name)
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
{
char sectionString[70];
genCenteredLabel(69, sectionString, name);
ccprintf(os, "====================================================================\n");
ccprintf(os, "%69s\n", sectionString);
ccprintf(os, "====================================================================\n");
}
inline void printLevelHeader(ostream & os, int level)
{
char sectionString[70];
char levelName[70];
sprintf(levelName, "Trap stack level %d", level);
genCenteredLabel(69, sectionString, levelName);
ccprintf(os, "====================================================================\n");
ccprintf(os, "%69s\n", sectionString);
ccprintf(os, "====================================================================\n");
}
void
Trace::LegionTraceRecord::dump()
{
ostream &outs = Trace::output();
static TheISA::Predecoder predecoder(NULL);
// Compare
bool compared = false;
bool diffPC = false;
bool diffCC = false;
bool diffInst = false;
bool diffIntRegs = false;
bool diffFpRegs = false;
bool diffTpc = false;
bool diffTnpc = false;
bool diffTstate = false;
bool diffTt = false;
bool diffTba = false;
bool diffHpstate = false;
bool diffHtstate = false;
bool diffHtba = false;
bool diffPstate = false;
bool diffY = false;
bool diffFsr = false;
bool diffCcr = false;
bool diffTl = false;
bool diffGl = false;
bool diffAsi = false;
bool diffPil = false;
bool diffCwp = false;
bool diffCansave = false;
bool diffCanrestore = false;
bool diffOtherwin = false;
bool diffCleanwin = false;
bool diffTlb = false;
Addr m5Pc, lgnPc;
if (!shared_data)
setupSharedData();
// We took a trap on a micro-op...
if (wasMicro && !staticInst->isMicroop())
{
// let's skip comparing this tick
while (!compared)
if (shared_data->flags == OWN_M5) {
shared_data->flags = OWN_LEGION;
compared = true;
}
compared = false;
wasMicro = false;
}
if (staticInst->isLastMicroop())
wasMicro = false;
else if (staticInst->isMicroop())
wasMicro = true;
if(!staticInst->isMicroop() || staticInst->isLastMicroop()) {
while (!compared) {
if (shared_data->flags == OWN_M5) {
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
m5Pc = pc.instAddr() & SparcISA::PAddrImplMask;
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
if (bits(shared_data->pstate,3,3)) {
m5Pc &= mask(32);
}
lgnPc = shared_data->pc & SparcISA::PAddrImplMask;
if (lgnPc != m5Pc)
diffPC = true;
if (shared_data->cycle_count !=
thread->getCpuPtr()->instCount())
diffCC = true;
if (shared_data->instruction !=
(SparcISA::MachInst)staticInst->machInst) {
diffInst = true;
}
// assume we have %g0 working correctly
for (int i = 1; i < TheISA::NumIntArchRegs; i++) {
if (thread->readIntReg(i) != shared_data->intregs[i]) {
diffIntRegs = true;
}
}
for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
Registers: Get rid of the float register width parameter.
2009-07-09 08:02:20 +02:00
if (thread->readFloatRegBits(i*2) !=
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
shared_data->fpregs[i]) {
diffFpRegs = true;
}
}
uint64_t oldTl =
thread->readMiscRegNoEffect(MISCREG_TL);
if (oldTl != shared_data->tl)
diffTl = true;
for (int i = 1; i <= MaxTL; i++) {
thread->setMiscRegNoEffect(MISCREG_TL, i);
if (thread->readMiscRegNoEffect(MISCREG_TPC) !=
shared_data->tpc[i-1])
diffTpc = true;
if (thread->readMiscRegNoEffect(MISCREG_TNPC) !=
shared_data->tnpc[i-1])
diffTnpc = true;
if (thread->readMiscRegNoEffect(MISCREG_TSTATE) !=
shared_data->tstate[i-1])
diffTstate = true;
if (thread->readMiscRegNoEffect(MISCREG_TT) !=
shared_data->tt[i-1])
diffTt = true;
if (thread->readMiscRegNoEffect(MISCREG_HTSTATE) !=
shared_data->htstate[i-1])
diffHtstate = true;
}
thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
if(shared_data->tba != thread->readMiscRegNoEffect(MISCREG_TBA))
diffTba = true;
//When the hpstate register is read by an instruction,
//legion has bit 11 set. When it's in storage, it doesn't.
//Since we don't directly support seperate interpretations
//of the registers like that, the bit is always set to 1 and
//we just don't compare it. It's not supposed to matter
//anyway.
if((shared_data->hpstate | (1 << 11)) !=
thread->readMiscRegNoEffect(MISCREG_HPSTATE))
diffHpstate = true;
if(shared_data->htba !=
thread->readMiscRegNoEffect(MISCREG_HTBA))
diffHtba = true;
if(shared_data->pstate !=
thread->readMiscRegNoEffect(MISCREG_PSTATE))
diffPstate = true;
//if(shared_data->y !=
// thread->readMiscRegNoEffect(MISCREG_Y))
if(shared_data->y !=
thread->readIntReg(NumIntArchRegs + 1))
diffY = true;
if(shared_data->fsr !=
thread->readMiscRegNoEffect(MISCREG_FSR)) {
diffFsr = true;
if (mbits(shared_data->fsr, 63,10) ==
mbits(thread->readMiscRegNoEffect(MISCREG_FSR),
63,10)) {
thread->setMiscRegNoEffect(MISCREG_FSR,
shared_data->fsr);
diffFsr = false;
}
}
//if(shared_data->ccr !=
// thread->readMiscRegNoEffect(MISCREG_CCR))
if(shared_data->ccr !=
thread->readIntReg(NumIntArchRegs + 2))
diffCcr = true;
if(shared_data->gl !=
thread->readMiscRegNoEffect(MISCREG_GL))
diffGl = true;
if(shared_data->asi !=
thread->readMiscRegNoEffect(MISCREG_ASI))
diffAsi = true;
if(shared_data->pil !=
thread->readMiscRegNoEffect(MISCREG_PIL))
diffPil = true;
if(shared_data->cwp !=
thread->readMiscRegNoEffect(MISCREG_CWP))
diffCwp = true;
//if(shared_data->cansave !=
// thread->readMiscRegNoEffect(MISCREG_CANSAVE))
if(shared_data->cansave !=
thread->readIntReg(NumIntArchRegs + 3))
diffCansave = true;
//if(shared_data->canrestore !=
// thread->readMiscRegNoEffect(MISCREG_CANRESTORE))
if(shared_data->canrestore !=
thread->readIntReg(NumIntArchRegs + 4))
diffCanrestore = true;
//if(shared_data->otherwin !=
// thread->readMiscRegNoEffect(MISCREG_OTHERWIN))
if(shared_data->otherwin !=
thread->readIntReg(NumIntArchRegs + 6))
diffOtherwin = true;
//if(shared_data->cleanwin !=
// thread->readMiscRegNoEffect(MISCREG_CLEANWIN))
if(shared_data->cleanwin !=
thread->readIntReg(NumIntArchRegs + 5))
diffCleanwin = true;
for (int i = 0; i < 64; i++) {
if (shared_data->itb[i] !=
thread->getITBPtr()->TteRead(i))
diffTlb = true;
if (shared_data->dtb[i] !=
thread->getDTBPtr()->TteRead(i))
diffTlb = true;
}
if (diffPC || diffCC || diffInst ||
diffIntRegs || diffFpRegs ||
diffTpc || diffTnpc || diffTstate || diffTt ||
diffHpstate || diffHtstate || diffHtba ||
diffPstate || diffY || diffCcr || diffTl || diffFsr ||
diffGl || diffAsi || diffPil || diffCwp ||
diffCansave || diffCanrestore ||
diffOtherwin || diffCleanwin || diffTlb) {
outs << "Differences found between M5 and Legion:";
if (diffPC)
outs << " [PC]";
if (diffCC)
outs << " [CC]";
if (diffInst)
outs << " [Instruction]";
if (diffIntRegs)
outs << " [IntRegs]";
if (diffFpRegs)
outs << " [FpRegs]";
if (diffTpc)
outs << " [Tpc]";
if (diffTnpc)
outs << " [Tnpc]";
if (diffTstate)
outs << " [Tstate]";
if (diffTt)
outs << " [Tt]";
if (diffHpstate)
outs << " [Hpstate]";
if (diffHtstate)
outs << " [Htstate]";
if (diffHtba)
outs << " [Htba]";
if (diffPstate)
outs << " [Pstate]";
if (diffY)
outs << " [Y]";
if (diffFsr)
outs << " [FSR]";
if (diffCcr)
outs << " [Ccr]";
if (diffTl)
outs << " [Tl]";
if (diffGl)
outs << " [Gl]";
if (diffAsi)
outs << " [Asi]";
if (diffPil)
outs << " [Pil]";
if (diffCwp)
outs << " [Cwp]";
if (diffCansave)
outs << " [Cansave]";
if (diffCanrestore)
outs << " [Canrestore]";
if (diffOtherwin)
outs << " [Otherwin]";
if (diffCleanwin)
outs << " [Cleanwin]";
if (diffTlb)
outs << " [Tlb]";
outs << endl << endl;
outs << right << setfill(' ') << setw(15)
<< "M5 PC: " << "0x"<< setw(16) << setfill('0')
<< hex << m5Pc << endl;
outs << setfill(' ') << setw(15)
<< "Legion PC: " << "0x"
<< setw(16) << setfill('0') << hex
<< lgnPc << endl << endl;
outs << right << setfill(' ') << setw(15)
<< "M5 CC: " << "0x"
<< setw(16) << setfill('0') << hex
<< thread->getCpuPtr()->instCount() << endl;
outs << setfill(' ') << setw(15)
<< "Legion CC: " << "0x"
<< setw(16) << setfill('0') << hex
<< shared_data->cycle_count << endl << endl;
outs << setfill(' ') << setw(15)
<< "M5 Inst: " << "0x"
<< setw(8) << setfill('0') << hex
<< staticInst->machInst
<< staticInst->disassemble(m5Pc, debugSymbolTable)
<< endl;
predecoder.setTC(thread);
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
predecoder.moreBytes(m5Pc, m5Pc, shared_data->instruction);
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
assert(predecoder.extMachInstReady());
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
PCState tempPC = pc;
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
StaticInstPtr legionInst =
Decode: Pull instruction decoding out of the StaticInst class into its own. This change pulls the instruction decoding machinery (including caches) out of the StaticInst class and puts it into its own class. This has a few intrinsic benefits. First, the StaticInst code, which has gotten to be quite large, gets simpler. Second, the code that handles decode caching is now separated out into its own component and can be looked at in isolation, making it easier to understand. I took the opportunity to restructure the code a bit which will hopefully also help. Beyond that, this change also lays some ground work for each ISA to have its own, potentially stateful decode object. We'd be able to include less contextualizing information in the ExtMachInst objects since that context would be applied at the decoder. Also, the decoder could "know" ahead of time that all the instructions it's going to see are going to be, for instance, 64 bit mode, and it will have one less thing to check when it decodes them. Because the decode caching mechanism has been separated out, it's now possible to have multiple caches which correspond to different types of decoding context. Having one cache for each element of the cross product of different configurations may become prohibitive, so it may be desirable to clear out the cache when relatively static state changes and not to have one for each setting. Because the decode function is no longer universally accessible as a static member of the StaticInst class, a new function was added to the ThreadContexts that returns the applicable decode object.
2011-09-09 11:30:01 +02:00
thread->getDecoderPtr()->decode(
predecoder.getExtMachInst(tempPC), lgnPc);
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
outs << setfill(' ') << setw(15)
<< " Legion Inst: "
<< "0x" << setw(8) << setfill('0') << hex
<< shared_data->instruction
<< legionInst->disassemble(lgnPc, debugSymbolTable)
<< endl << endl;
printSectionHeader(outs, "General State");
printColumnLabels(outs);
printRegPair(outs, "HPstate",
thread->readMiscRegNoEffect(MISCREG_HPSTATE),
shared_data->hpstate | (1 << 11));
printRegPair(outs, "Htba",
thread->readMiscRegNoEffect(MISCREG_HTBA),
shared_data->htba);
printRegPair(outs, "Pstate",
thread->readMiscRegNoEffect(MISCREG_PSTATE),
shared_data->pstate);
printRegPair(outs, "Y",
//thread->readMiscRegNoEffect(MISCREG_Y),
thread->readIntReg(NumIntArchRegs + 1),
shared_data->y);
printRegPair(outs, "FSR",
thread->readMiscRegNoEffect(MISCREG_FSR),
shared_data->fsr);
printRegPair(outs, "Ccr",
//thread->readMiscRegNoEffect(MISCREG_CCR),
thread->readIntReg(NumIntArchRegs + 2),
shared_data->ccr);
printRegPair(outs, "Tl",
thread->readMiscRegNoEffect(MISCREG_TL),
shared_data->tl);
printRegPair(outs, "Gl",
thread->readMiscRegNoEffect(MISCREG_GL),
shared_data->gl);
printRegPair(outs, "Asi",
thread->readMiscRegNoEffect(MISCREG_ASI),
shared_data->asi);
printRegPair(outs, "Pil",
thread->readMiscRegNoEffect(MISCREG_PIL),
shared_data->pil);
printRegPair(outs, "Cwp",
thread->readMiscRegNoEffect(MISCREG_CWP),
shared_data->cwp);
printRegPair(outs, "Cansave",
//thread->readMiscRegNoEffect(MISCREG_CANSAVE),
thread->readIntReg(NumIntArchRegs + 3),
shared_data->cansave);
printRegPair(outs, "Canrestore",
//thread->readMiscRegNoEffect(MISCREG_CANRESTORE),
thread->readIntReg(NumIntArchRegs + 4),
shared_data->canrestore);
printRegPair(outs, "Otherwin",
//thread->readMiscRegNoEffect(MISCREG_OTHERWIN),
thread->readIntReg(NumIntArchRegs + 6),
shared_data->otherwin);
printRegPair(outs, "Cleanwin",
//thread->readMiscRegNoEffect(MISCREG_CLEANWIN),
thread->readIntReg(NumIntArchRegs + 5),
shared_data->cleanwin);
outs << endl;
for (int i = 1; i <= MaxTL; i++) {
printLevelHeader(outs, i);
printColumnLabels(outs);
thread->setMiscRegNoEffect(MISCREG_TL, i);
printRegPair(outs, "Tpc",
thread->readMiscRegNoEffect(MISCREG_TPC),
shared_data->tpc[i-1]);
printRegPair(outs, "Tnpc",
thread->readMiscRegNoEffect(MISCREG_TNPC),
shared_data->tnpc[i-1]);
printRegPair(outs, "Tstate",
thread->readMiscRegNoEffect(MISCREG_TSTATE),
shared_data->tstate[i-1]);
printRegPair(outs, "Tt",
thread->readMiscRegNoEffect(MISCREG_TT),
shared_data->tt[i-1]);
printRegPair(outs, "Htstate",
thread->readMiscRegNoEffect(MISCREG_HTSTATE),
shared_data->htstate[i-1]);
}
thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
outs << endl;
printSectionHeader(outs, "General Purpose Registers");
static const char * regtypes[4] =
{"%g", "%o", "%l", "%i"};
for(int y = 0; y < 4; y++) {
for(int x = 0; x < 8; x++) {
char label[8];
sprintf(label, "%s%d", regtypes[y], x);
printRegPair(outs, label,
thread->readIntReg(y*8+x),
shared_data->intregs[y*8+x]);
}
}
if (diffFpRegs) {
for (int x = 0; x < 32; x++) {
char label[8];
sprintf(label, "%%f%d", x);
printRegPair(outs, label,
Registers: Get rid of the float register width parameter.
2009-07-09 08:02:20 +02:00
thread->readFloatRegBits(x*2),
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
shared_data->fpregs[x]);
}
}
if (diffTlb) {
printColumnLabels(outs);
char label[8];
for (int x = 0; x < 64; x++) {
if (shared_data->itb[x] !=
ULL(0xFFFFFFFFFFFFFFFF) ||
thread->getITBPtr()->TteRead(x) !=
ULL(0xFFFFFFFFFFFFFFFF)) {
sprintf(label, "I-TLB:%02d", x);
printRegPair(outs, label,
thread->getITBPtr()->TteRead(x),
shared_data->itb[x]);
}
}
for (int x = 0; x < 64; x++) {
if (shared_data->dtb[x] !=
ULL(0xFFFFFFFFFFFFFFFF) ||
thread->getDTBPtr()->TteRead(x) !=
ULL(0xFFFFFFFFFFFFFFFF)) {
sprintf(label, "D-TLB:%02d", x);
printRegPair(outs, label,
thread->getDTBPtr()->TteRead(x),
shared_data->dtb[x]);
}
}
thread->getITBPtr()->dumpAll();
thread->getDTBPtr()->dumpAll();
}
diffcount++;
if (diffcount > 3)
fatal("Differences found between Legion and M5\n");
} else
diffcount = 0;
compared = true;
shared_data->flags = OWN_LEGION;
}
} // while
} // if not microop
}
Make commenting on close namespace brackets consistent. Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript.
2011-01-03 23:35:43 +01:00
} // namespace Trace
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
////////////////////////////////////////////////////////////////////////
//
// ExeTracer Simulation Object
//
Trace::LegionTrace *
LegionTraceParams::create()
{
params: Deprecate old-style constructors; update most SimObject constructors. SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) --HG-- extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
2007-08-30 21:16:59 +02:00
return new Trace::LegionTrace(this);
Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-29 05:30:43 +02:00
};
Reference in a new issue Copy permalink