2008-11-06 00:10:30 +01:00
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---------- Begin Simulation Statistics ----------
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2009-04-09 07:21:30 +02:00
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host_inst_rate 4748415 # Simulator instruction rate (inst/s)
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host_mem_usage 1125700 # Number of bytes of host memory used
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host_seconds 0.42 # Real time elapsed on the host
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host_tick_rate 593193174 # Simulator tick rate (ticks/s)
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2008-11-06 00:10:30 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 2000004 # Number of instructions simulated
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sim_seconds 0.000250 # Number of seconds simulated
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sim_ticks 250015500 # Number of ticks simulated
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system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
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system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses
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system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
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system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
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system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
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system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits
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system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
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system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses
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system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
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system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
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system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
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system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu0.dcache.overall_hits 180140 # number of overall hits
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system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
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system.cpu0.dcache.overall_misses 635 # number of overall misses
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system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
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system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
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system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu0.dcache.replacements 61 # number of replacements
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system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
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system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use
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system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
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system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.writebacks 29 # number of writebacks
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2009-04-09 07:21:30 +02:00
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system.cpu0.dtb.data_accesses 180793 # DTB accesses
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system.cpu0.dtb.data_acv 0 # DTB access violations
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system.cpu0.dtb.data_hits 180775 # DTB hits
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system.cpu0.dtb.data_misses 18 # DTB misses
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system.cpu0.dtb.fetch_accesses 0 # ITB accesses
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system.cpu0.dtb.fetch_acv 0 # ITB acv
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system.cpu0.dtb.fetch_hits 0 # ITB hits
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system.cpu0.dtb.fetch_misses 0 # ITB misses
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2008-11-06 00:10:30 +01:00
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system.cpu0.dtb.read_accesses 124443 # DTB read accesses
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system.cpu0.dtb.read_acv 0 # DTB read access violations
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system.cpu0.dtb.read_hits 124435 # DTB read hits
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system.cpu0.dtb.read_misses 8 # DTB read misses
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system.cpu0.dtb.write_accesses 56350 # DTB write accesses
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system.cpu0.dtb.write_acv 0 # DTB write access violations
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system.cpu0.dtb.write_hits 56340 # DTB write hits
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system.cpu0.dtb.write_misses 10 # DTB write misses
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system.cpu0.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.ReadReq_hits 499556 # number of ReadReq hits
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system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
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system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
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system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.demand_accesses 500019 # number of demand (read+write) accesses
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system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency
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system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
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system.cpu0.icache.demand_hits 499556 # number of demand (read+write) hits
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system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
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system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
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system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
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system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
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system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
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system.cpu0.icache.fast_writes 0 # number of fast writes performed
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system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses
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system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency
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system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu0.icache.overall_hits 499556 # number of overall hits
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system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
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system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
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system.cpu0.icache.overall_misses 463 # number of overall misses
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system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
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system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
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system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
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system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu0.icache.replacements 152 # number of replacements
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system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
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system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use
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system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks.
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system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.writebacks 0 # number of writebacks
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system.cpu0.idle_fraction 0 # Percentage of idle cycles
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2009-04-09 07:21:30 +02:00
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system.cpu0.itb.data_accesses 0 # DTB accesses
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system.cpu0.itb.data_acv 0 # DTB access violations
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system.cpu0.itb.data_hits 0 # DTB hits
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system.cpu0.itb.data_misses 0 # DTB misses
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system.cpu0.itb.fetch_accesses 500032 # ITB accesses
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system.cpu0.itb.fetch_acv 0 # ITB acv
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system.cpu0.itb.fetch_hits 500019 # ITB hits
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system.cpu0.itb.fetch_misses 13 # ITB misses
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system.cpu0.itb.read_accesses 0 # DTB read accesses
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system.cpu0.itb.read_acv 0 # DTB read access violations
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system.cpu0.itb.read_hits 0 # DTB read hits
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system.cpu0.itb.read_misses 0 # DTB read misses
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system.cpu0.itb.write_accesses 0 # DTB write accesses
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system.cpu0.itb.write_acv 0 # DTB write access violations
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system.cpu0.itb.write_hits 0 # DTB write hits
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system.cpu0.itb.write_misses 0 # DTB write misses
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2008-11-06 00:10:30 +01:00
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system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu0.numCycles 500032 # number of cpu cycles simulated
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system.cpu0.num_insts 500001 # Number of instructions executed
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system.cpu0.num_refs 182222 # Number of memory references
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system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls
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system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
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system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits
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system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
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system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
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system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
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system.cpu1.dcache.WriteReq_hits 56029 # number of WriteReq hits
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system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
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system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses
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system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
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system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses
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system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency
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system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
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system.cpu1.dcache.demand_hits 180140 # number of demand (read+write) hits
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system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
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system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
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system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses
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system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
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system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
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system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
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system.cpu1.dcache.fast_writes 0 # number of fast writes performed
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system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses
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system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
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system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
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system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu1.dcache.overall_hits 180140 # number of overall hits
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system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
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system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
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system.cpu1.dcache.overall_misses 635 # number of overall misses
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system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
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system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
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system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
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system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu1.dcache.replacements 61 # number of replacements
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system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
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system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use
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system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks.
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system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu1.dcache.writebacks 29 # number of writebacks
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2009-04-09 07:21:30 +02:00
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system.cpu1.dtb.data_accesses 180793 # DTB accesses
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system.cpu1.dtb.data_acv 0 # DTB access violations
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system.cpu1.dtb.data_hits 180775 # DTB hits
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|
|
system.cpu1.dtb.data_misses 18 # DTB misses
|
|
|
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
|
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
2008-11-06 00:10:30 +01:00
|
|
|
system.cpu1.dtb.read_accesses 124443 # DTB read accesses
|
|
|
|
|
system.cpu1.dtb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu1.dtb.read_hits 124435 # DTB read hits
|
|
|
|
|
system.cpu1.dtb.read_misses 8 # DTB read misses
|
|
|
|
|
system.cpu1.dtb.write_accesses 56350 # DTB write accesses
|
|
|
|
|
system.cpu1.dtb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu1.dtb.write_hits 56340 # DTB write hits
|
|
|
|
|
system.cpu1.dtb.write_misses 10 # DTB write misses
|
|
|
|
|
system.cpu1.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.icache.ReadReq_hits 499556 # number of ReadReq hits
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses
|
|
|
|
|
system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu1.icache.demand_accesses 500019 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.demand_hits 499556 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu1.icache.overall_hits 499556 # number of overall hits
|
|
|
|
|
system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
|
|
|
|
|
system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.overall_misses 463 # number of overall misses
|
|
|
|
|
system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu1.icache.replacements 152 # number of replacements
|
|
|
|
|
system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu1.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu1.idle_fraction 0 # Percentage of idle cycles
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu1.itb.fetch_accesses 500032 # ITB accesses
|
|
|
|
|
system.cpu1.itb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu1.itb.fetch_hits 500019 # ITB hits
|
|
|
|
|
system.cpu1.itb.fetch_misses 13 # ITB misses
|
|
|
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
2008-11-06 00:10:30 +01:00
|
|
|
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu1.numCycles 500032 # number of cpu cycles simulated
|
|
|
|
|
system.cpu1.num_insts 500001 # Number of instructions executed
|
|
|
|
|
system.cpu1.num_refs 182222 # Number of memory references
|
|
|
|
|
system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls
|
|
|
|
|
system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits
|
|
|
|
|
system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
|
|
|
|
|
system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits
|
|
|
|
|
system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses
|
|
|
|
|
system.cpu2.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency
|
|
|
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
|
|
|
system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits
|
|
|
|
|
system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
|
|
|
|
|
system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses
|
|
|
|
|
system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency
|
|
|
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
|
|
|
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu2.dcache.overall_hits 180140 # number of overall hits
|
|
|
|
|
system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles
|
|
|
|
|
system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
|
|
|
|
|
system.cpu2.dcache.overall_misses 635 # number of overall misses
|
|
|
|
|
system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
|
|
|
system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu2.dcache.replacements 61 # number of replacements
|
|
|
|
|
system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use
|
|
|
|
|
system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu2.dcache.writebacks 29 # number of writebacks
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu2.dtb.data_accesses 180793 # DTB accesses
|
|
|
|
|
system.cpu2.dtb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu2.dtb.data_hits 180775 # DTB hits
|
|
|
|
|
system.cpu2.dtb.data_misses 18 # DTB misses
|
|
|
|
|
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
|
|
|
|
|
system.cpu2.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu2.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu2.dtb.fetch_misses 0 # ITB misses
|
2008-11-06 00:10:30 +01:00
|
|
|
system.cpu2.dtb.read_accesses 124443 # DTB read accesses
|
|
|
|
|
system.cpu2.dtb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu2.dtb.read_hits 124435 # DTB read hits
|
|
|
|
|
system.cpu2.dtb.read_misses 8 # DTB read misses
|
|
|
|
|
system.cpu2.dtb.write_accesses 56350 # DTB write accesses
|
|
|
|
|
system.cpu2.dtb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu2.dtb.write_hits 56340 # DTB write hits
|
|
|
|
|
system.cpu2.dtb.write_misses 10 # DTB write misses
|
|
|
|
|
system.cpu2.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu2.icache.ReadReq_hits 499556 # number of ReadReq hits
|
|
|
|
|
system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses
|
|
|
|
|
system.cpu2.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu2.icache.demand_accesses 500019 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency
|
|
|
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
|
|
|
system.cpu2.icache.demand_hits 499556 # number of demand (read+write) hits
|
|
|
|
|
system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
|
|
|
|
|
system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses
|
|
|
|
|
system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency
|
|
|
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
|
|
|
system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu2.icache.overall_hits 499556 # number of overall hits
|
|
|
|
|
system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles
|
|
|
|
|
system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
|
|
|
|
|
system.cpu2.icache.overall_misses 463 # number of overall misses
|
|
|
|
|
system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
|
|
|
system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu2.icache.replacements 152 # number of replacements
|
|
|
|
|
system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use
|
|
|
|
|
system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu2.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu2.idle_fraction 0 # Percentage of idle cycles
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu2.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu2.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu2.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu2.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu2.itb.fetch_accesses 500032 # ITB accesses
|
|
|
|
|
system.cpu2.itb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu2.itb.fetch_hits 500019 # ITB hits
|
|
|
|
|
system.cpu2.itb.fetch_misses 13 # ITB misses
|
|
|
|
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu2.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu2.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
2008-11-06 00:10:30 +01:00
|
|
|
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu2.numCycles 500032 # number of cpu cycles simulated
|
|
|
|
|
system.cpu2.num_insts 500001 # Number of instructions executed
|
|
|
|
|
system.cpu2.num_refs 182222 # Number of memory references
|
|
|
|
|
system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls
|
|
|
|
|
system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits
|
|
|
|
|
system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
|
|
|
|
|
system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu3.dcache.WriteReq_hits 56029 # number of WriteReq hits
|
|
|
|
|
system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses
|
|
|
|
|
system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency
|
|
|
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
|
|
|
system.cpu3.dcache.demand_hits 180140 # number of demand (read+write) hits
|
|
|
|
|
system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
|
|
|
|
|
system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses
|
|
|
|
|
system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency
|
|
|
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
|
|
|
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu3.dcache.overall_hits 180140 # number of overall hits
|
|
|
|
|
system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles
|
|
|
|
|
system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
|
|
|
|
|
system.cpu3.dcache.overall_misses 635 # number of overall misses
|
|
|
|
|
system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
|
|
|
system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu3.dcache.replacements 61 # number of replacements
|
|
|
|
|
system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use
|
|
|
|
|
system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu3.dcache.writebacks 29 # number of writebacks
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu3.dtb.data_accesses 180793 # DTB accesses
|
|
|
|
|
system.cpu3.dtb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu3.dtb.data_hits 180775 # DTB hits
|
|
|
|
|
system.cpu3.dtb.data_misses 18 # DTB misses
|
|
|
|
|
system.cpu3.dtb.fetch_accesses 0 # ITB accesses
|
|
|
|
|
system.cpu3.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu3.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu3.dtb.fetch_misses 0 # ITB misses
|
2008-11-06 00:10:30 +01:00
|
|
|
system.cpu3.dtb.read_accesses 124443 # DTB read accesses
|
|
|
|
|
system.cpu3.dtb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu3.dtb.read_hits 124435 # DTB read hits
|
|
|
|
|
system.cpu3.dtb.read_misses 8 # DTB read misses
|
|
|
|
|
system.cpu3.dtb.write_accesses 56350 # DTB write accesses
|
|
|
|
|
system.cpu3.dtb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu3.dtb.write_hits 56340 # DTB write hits
|
|
|
|
|
system.cpu3.dtb.write_misses 10 # DTB write misses
|
|
|
|
|
system.cpu3.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu3.icache.ReadReq_hits 499556 # number of ReadReq hits
|
|
|
|
|
system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses
|
|
|
|
|
system.cpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu3.icache.demand_accesses 500019 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency
|
|
|
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
|
|
|
system.cpu3.icache.demand_hits 499556 # number of demand (read+write) hits
|
|
|
|
|
system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
|
|
|
|
|
system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses
|
|
|
|
|
system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency
|
|
|
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
|
|
|
system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu3.icache.overall_hits 499556 # number of overall hits
|
|
|
|
|
system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles
|
|
|
|
|
system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
|
|
|
|
|
system.cpu3.icache.overall_misses 463 # number of overall misses
|
|
|
|
|
system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
|
|
|
system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu3.icache.replacements 152 # number of replacements
|
|
|
|
|
system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use
|
|
|
|
|
system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu3.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu3.idle_fraction 0 # Percentage of idle cycles
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu3.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu3.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu3.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu3.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu3.itb.fetch_accesses 500032 # ITB accesses
|
|
|
|
|
system.cpu3.itb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu3.itb.fetch_hits 500019 # ITB hits
|
|
|
|
|
system.cpu3.itb.fetch_misses 13 # ITB misses
|
|
|
|
|
system.cpu3.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu3.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu3.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu3.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu3.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu3.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu3.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu3.itb.write_misses 0 # DTB write misses
|
2008-11-06 00:10:30 +01:00
|
|
|
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu3.numCycles 500032 # number of cpu cycles simulated
|
|
|
|
|
system.cpu3.num_insts 500001 # Number of instructions executed
|
|
|
|
|
system.cpu3.num_refs 182222 # Number of memory references
|
|
|
|
|
system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls
|
|
|
|
|
system.l2c.ReadExReq_accesses 556 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_misses 556 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadReq_accesses 3148 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_hits 276 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_miss_rate 0.912325 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_misses 2872 # number of ReadReq misses
|
|
|
|
|
system.l2c.UpgradeReq_accesses 688 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_hits 116 # number of Writeback hits
|
|
|
|
|
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_refs 0.120000 # Average number of references to valid blocks.
|
|
|
|
|
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.l2c.demand_accesses 3704 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_avg_miss_latency 0 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_hits 276 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_misses 3428 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.l2c.overall_accesses 3704 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_avg_miss_latency 0 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.l2c.overall_hits 276 # number of overall hits
|
|
|
|
|
system.l2c.overall_miss_latency 0 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_misses 3428 # number of overall misses
|
|
|
|
|
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.l2c.replacements 0 # number of replacements
|
|
|
|
|
system.l2c.sampled_refs 2300 # Sample count of references to valid blocks.
|
|
|
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.l2c.tagsinuse 1529.374598 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 276 # Total number of references to valid blocks.
|
|
|
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.l2c.writebacks 0 # number of writebacks
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
