2009-02-11 00:49:29 +01:00
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/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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2009-05-26 18:23:13 +02:00
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#include <algorithm>
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2009-04-18 01:54:58 +02:00
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2009-02-11 00:49:29 +01:00
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#include "arch/utility.hh"
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2009-05-26 18:23:13 +02:00
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#include "config/full_system.hh"
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2009-02-11 00:49:29 +01:00
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#include "cpu/exetrace.hh"
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#include "cpu/activity.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/base.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/thread_context.hh"
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#include "cpu/inorder/thread_state.hh"
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#include "cpu/inorder/cpu.hh"
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#include "params/InOrderCPU.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/first_stage.hh"
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#include "cpu/inorder/resources/resource_list.hh"
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#include "cpu/inorder/resource_pool.hh"
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#include "mem/translating_port.hh"
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#include "sim/process.hh"
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#include "sim/stat_control.hh"
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using namespace std;
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using namespace TheISA;
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using namespace ThePipeline;
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InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
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: Event(CPU_Tick_Pri), cpu(c)
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{ }
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void
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InOrderCPU::TickEvent::process()
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{
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cpu->tick();
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}
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const char *
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InOrderCPU::TickEvent::description()
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{
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return "InOrderCPU tick event";
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}
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InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
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2009-05-26 18:23:13 +02:00
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Fault fault, ThreadID _tid, unsigned _vpe)
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2009-02-11 00:49:29 +01:00
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: Event(CPU_Tick_Pri), cpu(_cpu)
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{
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setEvent(e_type, fault, _tid, _vpe);
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}
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2009-05-12 21:01:16 +02:00
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std::string InOrderCPU::eventNames[NumCPUEvents] =
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{
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"ActivateThread",
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"DeallocateThread",
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"SuspendThread",
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"DisableThreads",
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"EnableThreads",
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"DisableVPEs",
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"EnableVPEs",
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"Trap",
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"InstGraduated",
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"SquashAll",
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"UpdatePCs"
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};
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2009-02-11 00:49:29 +01:00
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void
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InOrderCPU::CPUEvent::process()
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{
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switch (cpuEventType)
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{
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case ActivateThread:
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cpu->activateThread(tid);
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break;
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//@TODO: Consider Implementing "Suspend Thread" as Separate from Deallocate
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case SuspendThread: // Suspend & Deallocate are same for now.
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//cpu->suspendThread(tid);
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//break;
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case DeallocateThread:
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cpu->deallocateThread(tid);
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break;
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case EnableVPEs:
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cpu->enableVPEs(vpe);
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break;
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case DisableVPEs:
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cpu->disableVPEs(tid, vpe);
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break;
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case EnableThreads:
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cpu->enableThreads(vpe);
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break;
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case DisableThreads:
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cpu->disableThreads(tid, vpe);
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break;
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case Trap:
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cpu->trapCPU(fault, tid);
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break;
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default:
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fatal("Unrecognized Event Type %d", cpuEventType);
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}
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cpu->cpuEventRemoveList.push(this);
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}
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const char *
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InOrderCPU::CPUEvent::description()
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{
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return "InOrderCPU event";
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}
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void
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InOrderCPU::CPUEvent::scheduleEvent(int delay)
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{
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if (squashed())
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mainEventQueue.reschedule(this,curTick + cpu->ticks(delay));
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else if (!scheduled())
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mainEventQueue.schedule(this,curTick + cpu->ticks(delay));
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}
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void
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InOrderCPU::CPUEvent::unscheduleEvent()
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{
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if (scheduled())
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squash();
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}
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InOrderCPU::InOrderCPU(Params *params)
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: BaseCPU(params),
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cpu_id(params->cpu_id),
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2009-03-05 04:37:45 +01:00
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coreType("default"),
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_status(Idle),
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2009-02-11 00:49:29 +01:00
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tickEvent(this),
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miscRegFile(this),
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timeBuffer(2 , 2),
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removeInstsThisCycle(false),
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activityRec(params->name, NumStages, 10, params->activity),
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switchCount(0),
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deferRegistration(false/*params->deferRegistration*/),
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stageTracing(params->stageTracing),
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numVirtProcs(1)
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{
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cpu_params = params;
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resPool = new ResourcePool(this, params);
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// Resize for Multithreading CPUs
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thread.resize(numThreads);
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int active_threads = params->workload.size();
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if (active_threads > MaxThreads) {
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panic("Workload Size too large. Increase the 'MaxThreads'"
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"in your InOrder implementation or "
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"edit your workload size.");
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}
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// Bind the fetch & data ports from the resource pool.
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fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
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if (fetchPortIdx == 0) {
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2009-05-12 21:01:13 +02:00
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fatal("Unable to find port to fetch instructions from.\n");
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2009-02-11 00:49:29 +01:00
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}
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dataPortIdx = resPool->getPortIdx(params->dataMemPort);
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if (dataPortIdx == 0) {
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2009-05-12 21:01:13 +02:00
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fatal("Unable to find port for data.\n");
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2009-02-11 00:49:29 +01:00
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}
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2009-05-26 18:23:13 +02:00
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for (ThreadID tid = 0; tid < numThreads; ++tid) {
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if (tid < params->workload.size()) {
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2009-03-04 19:17:08 +01:00
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DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
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2009-05-26 18:23:13 +02:00
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tid, this->thread[tid]);
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this->thread[tid] =
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new Thread(this, tid, params->workload[tid], tid);
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2009-02-11 00:49:29 +01:00
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} else {
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//Allocate Empty thread so M5 can use later
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//when scheduling threads to CPU
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2009-03-04 19:17:08 +01:00
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Process* dummy_proc = params->workload[0];
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2009-05-26 18:23:13 +02:00
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this->thread[tid] = new Thread(this, tid, dummy_proc, tid);
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2009-02-11 00:49:29 +01:00
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}
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// Setup the TC that will serve as the interface to the threads/CPU.
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InOrderThreadContext *tc = new InOrderThreadContext;
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tc->cpu = this;
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2009-05-26 18:23:13 +02:00
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tc->thread = thread[tid];
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2009-02-11 00:49:29 +01:00
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// Give the thread the TC.
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2009-05-26 18:23:13 +02:00
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thread[tid]->tc = tc;
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thread[tid]->setFuncExeInst(0);
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globalSeqNum[tid] = 1;
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2009-02-11 00:49:29 +01:00
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// Add the TC to the CPU's list of TC's.
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this->threadContexts.push_back(tc);
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}
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// Initialize TimeBuffer Stage Queues
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for (int stNum=0; stNum < NumStages - 1; stNum++) {
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stageQueue[stNum] = new StageQueue(NumStages, NumStages);
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2009-03-04 19:16:49 +01:00
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stageQueue[stNum]->id(stNum);
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2009-02-11 00:49:29 +01:00
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}
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// Set Up Pipeline Stages
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for (int stNum=0; stNum < NumStages; stNum++) {
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if (stNum == 0)
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pipelineStage[stNum] = new FirstStage(params, stNum);
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else
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pipelineStage[stNum] = new PipelineStage(params, stNum);
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pipelineStage[stNum]->setCPU(this);
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pipelineStage[stNum]->setActiveThreads(&activeThreads);
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pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
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// Take Care of 1st/Nth stages
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if (stNum > 0)
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pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
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2009-03-04 19:17:07 +01:00
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if (stNum < NumStages - 1)
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pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
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2009-02-11 00:49:29 +01:00
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}
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// Initialize thread specific variables
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2009-05-26 18:23:13 +02:00
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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2009-02-11 00:49:29 +01:00
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archRegDepMap[tid].setCPU(this);
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nonSpecInstActive[tid] = false;
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nonSpecSeqNum[tid] = 0;
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squashSeqNum[tid] = MaxAddr;
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lastSquashCycle[tid] = 0;
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intRegFile[tid].clear();
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floatRegFile[tid].clear();
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}
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// Update miscRegFile if necessary
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if (numThreads > 1) {
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miscRegFile.expandForMultithreading(numThreads, numVirtProcs);
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}
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miscRegFile.clear();
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lastRunningCycle = curTick;
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contextSwitch = false;
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// Define dummy instructions and resource requests to be used.
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DynInstPtr dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0);
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dummyReq = new ResourceRequest(NULL, NULL, 0, 0, 0, 0);
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// Reset CPU to reset state.
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#if FULL_SYSTEM
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Fault resetFault = new ResetFault();
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resetFault->invoke(tcBase());
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#else
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reset();
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#endif
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// Schedule First Tick Event, CPU will reschedule itself from here on out.
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scheduleTickEvent(0);
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}
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void
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InOrderCPU::regStats()
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{
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/* Register the Resource Pool's stats here.*/
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resPool->regStats();
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/* Register any of the InOrderCPU's stats here.*/
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timesIdled
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.name(name() + ".timesIdled")
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.desc("Number of times that the entire CPU went into an idle state and"
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" unscheduled itself")
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.prereq(timesIdled);
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idleCycles
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.name(name() + ".idleCycles")
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.desc("Total number of cycles that the CPU has spent unscheduled due "
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"to idling")
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.prereq(idleCycles);
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threadCycles
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.init(numThreads)
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.name(name() + ".threadCycles")
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.desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
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smtCycles
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.name(name() + ".smtCycles")
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.desc("Total number of cycles that the CPU was simultaneous multithreading.(SMT)");
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committedInsts
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.init(numThreads)
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.name(name() + ".committedInsts")
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.desc("Number of Instructions Simulated (Per-Thread)");
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smtCommittedInsts
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.init(numThreads)
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.name(name() + ".smtCommittedInsts")
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.desc("Number of SMT Instructions Simulated (Per-Thread)");
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totalCommittedInsts
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.name(name() + ".committedInsts_total")
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.desc("Number of Instructions Simulated (Total)");
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cpi
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.name(name() + ".cpi")
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.desc("CPI: Cycles Per Instruction (Per-Thread)")
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.precision(6);
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cpi = threadCycles / committedInsts;
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smtCpi
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.name(name() + ".smt_cpi")
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.desc("CPI: Total SMT-CPI")
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.precision(6);
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smtCpi = smtCycles / smtCommittedInsts;
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totalCpi
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.name(name() + ".cpi_total")
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.desc("CPI: Total CPI of All Threads")
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.precision(6);
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2009-03-04 19:16:48 +01:00
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totalCpi = numCycles / totalCommittedInsts;
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2009-02-11 00:49:29 +01:00
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ipc
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.name(name() + ".ipc")
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.desc("IPC: Instructions Per Cycle (Per-Thread)")
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.precision(6);
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ipc = committedInsts / threadCycles;
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|
|
|
smtIpc
|
|
|
|
.name(name() + ".smt_ipc")
|
|
|
|
.desc("IPC: Total SMT-IPC")
|
|
|
|
.precision(6);
|
|
|
|
smtIpc = smtCommittedInsts / smtCycles;
|
|
|
|
|
|
|
|
totalIpc
|
|
|
|
.name(name() + ".ipc_total")
|
|
|
|
.desc("IPC: Total IPC of All Threads")
|
|
|
|
.precision(6);
|
2009-03-04 19:16:48 +01:00
|
|
|
totalIpc = totalCommittedInsts / numCycles;
|
2009-02-11 00:49:29 +01:00
|
|
|
|
|
|
|
BaseCPU::regStats();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::tick()
|
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
|
|
|
|
|
|
|
|
++numCycles;
|
|
|
|
|
|
|
|
//Tick each of the stages
|
|
|
|
for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
|
|
|
|
pipelineStage[stNum]->tick();
|
|
|
|
}
|
|
|
|
|
|
|
|
// Now advance the time buffers one tick
|
|
|
|
timeBuffer.advance();
|
|
|
|
for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
|
|
|
|
stageQueue[sqNum]->advance();
|
|
|
|
}
|
|
|
|
activityRec.advance();
|
|
|
|
|
|
|
|
// Any squashed requests, events, or insts then remove them now
|
|
|
|
cleanUpRemovedReqs();
|
|
|
|
cleanUpRemovedEvents();
|
|
|
|
cleanUpRemovedInsts();
|
|
|
|
|
|
|
|
// Re-schedule CPU for this cycle
|
|
|
|
if (!tickEvent.scheduled()) {
|
|
|
|
if (_status == SwitchedOut) {
|
|
|
|
// increment stat
|
|
|
|
lastRunningCycle = curTick;
|
|
|
|
} else if (!activityRec.active()) {
|
|
|
|
DPRINTF(InOrderCPU, "sleeping CPU.\n");
|
|
|
|
lastRunningCycle = curTick;
|
|
|
|
timesIdled++;
|
|
|
|
} else {
|
|
|
|
//Tick next_tick = curTick + cycles(1);
|
|
|
|
//tickEvent.schedule(next_tick);
|
|
|
|
mainEventQueue.schedule(&tickEvent, nextCycle(curTick + 1));
|
|
|
|
DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n", nextCycle() + curTick);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
tickThreadStats();
|
|
|
|
updateThreadPriority();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::init()
|
|
|
|
{
|
|
|
|
if (!deferRegistration) {
|
|
|
|
registerThreadContexts();
|
|
|
|
}
|
|
|
|
|
|
|
|
// Set inSyscall so that the CPU doesn't squash when initially
|
|
|
|
// setting up registers.
|
2009-05-26 18:23:13 +02:00
|
|
|
for (ThreadID tid = 0; tid < numThreads; ++tid)
|
|
|
|
thread[tid]->inSyscall = true;
|
2009-02-11 00:49:29 +01:00
|
|
|
|
2009-04-18 01:54:58 +02:00
|
|
|
#if FULL_SYSTEM
|
2009-05-26 18:23:13 +02:00
|
|
|
for (ThreadID tid = 0; tid < numThreads; tid++) {
|
2009-04-18 01:54:58 +02:00
|
|
|
ThreadContext *src_tc = threadContexts[tid];
|
|
|
|
TheISA::initCPU(src_tc, src_tc->contextId());
|
2009-02-11 00:49:29 +01:00
|
|
|
}
|
2009-04-18 01:54:58 +02:00
|
|
|
#endif
|
2009-02-11 00:49:29 +01:00
|
|
|
|
|
|
|
// Clear inSyscall.
|
2009-05-26 18:23:13 +02:00
|
|
|
for (ThreadID tid = 0; tid < numThreads; ++tid)
|
|
|
|
thread[tid]->inSyscall = false;
|
2009-02-11 00:49:29 +01:00
|
|
|
|
|
|
|
// Call Initializiation Routine for Resource Pool
|
|
|
|
resPool->init();
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::readFunctional(Addr addr, uint32_t &buffer)
|
|
|
|
{
|
|
|
|
tcBase()->getMemPort()->readBlob(addr, (uint8_t*)&buffer, sizeof(uint32_t));
|
|
|
|
buffer = gtoh(buffer);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::reset()
|
|
|
|
{
|
|
|
|
miscRegFile.reset(coreType, numThreads, numVirtProcs, dynamic_cast<BaseCPU*>(this));
|
|
|
|
}
|
|
|
|
|
|
|
|
Port*
|
|
|
|
InOrderCPU::getPort(const std::string &if_name, int idx)
|
|
|
|
{
|
|
|
|
return resPool->getPort(if_name, idx);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::trap(Fault fault, ThreadID tid, int delay)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
2009-05-12 21:01:16 +02:00
|
|
|
//@ Squash Pipeline during TRAP
|
2009-02-11 00:49:29 +01:00
|
|
|
scheduleCpuEvent(Trap, fault, tid, 0/*vpe*/, delay);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::trapCPU(Fault fault, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
fault->invoke(tcBase(tid));
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
|
2009-05-26 18:23:13 +02:00
|
|
|
ThreadID tid, unsigned vpe, unsigned delay)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, vpe);
|
|
|
|
|
|
|
|
if (delay >= 0) {
|
2009-05-12 21:01:16 +02:00
|
|
|
DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i.\n",
|
2009-05-12 21:01:16 +02:00
|
|
|
eventNames[c_event], curTick + delay);
|
2009-02-11 00:49:29 +01:00
|
|
|
mainEventQueue.schedule(cpu_event,curTick + delay);
|
|
|
|
} else {
|
|
|
|
cpu_event->process();
|
|
|
|
cpuEventRemoveList.push(cpu_event);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Broadcast event to the Resource Pool
|
2009-05-26 18:23:13 +02:00
|
|
|
DynInstPtr dummy_inst =
|
|
|
|
new InOrderDynInst(this, NULL, getNextEventNum(), tid);
|
2009-02-11 00:49:29 +01:00
|
|
|
resPool->scheduleEvent(c_event, dummy_inst, 0, 0, tid);
|
|
|
|
}
|
|
|
|
|
|
|
|
inline bool
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::isThreadActive(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
2009-05-26 18:23:13 +02:00
|
|
|
list<ThreadID>::iterator isActive =
|
|
|
|
std::find(activeThreads.begin(), activeThreads.end(), tid);
|
2009-02-11 00:49:29 +01:00
|
|
|
|
|
|
|
return (isActive != activeThreads.end());
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::activateThread(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
if (!isThreadActive(tid)) {
|
2009-05-26 18:23:13 +02:00
|
|
|
DPRINTF(InOrderCPU,
|
|
|
|
"Adding Thread %i to active threads list in CPU.\n", tid);
|
2009-02-11 00:49:29 +01:00
|
|
|
activeThreads.push_back(tid);
|
|
|
|
|
|
|
|
wakeCPU();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::deactivateThread(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
|
|
|
|
|
|
|
|
if (isThreadActive(tid)) {
|
|
|
|
DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
|
|
|
|
tid);
|
2009-05-26 18:23:13 +02:00
|
|
|
list<ThreadID>::iterator thread_it =
|
|
|
|
std::find(activeThreads.begin(), activeThreads.end(), tid);
|
2009-02-11 00:49:29 +01:00
|
|
|
|
|
|
|
removePipelineStalls(*thread_it);
|
|
|
|
|
|
|
|
//@TODO: change stage status' to Idle?
|
|
|
|
|
|
|
|
activeThreads.erase(thread_it);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::removePipelineStalls(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
|
|
|
|
tid);
|
|
|
|
|
|
|
|
for (int stNum = 0; stNum < NumStages ; stNum++) {
|
|
|
|
pipelineStage[stNum]->removeStalls(tid);
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
bool
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::isThreadInCPU(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
2009-05-26 18:23:13 +02:00
|
|
|
list<ThreadID>::iterator isCurrent =
|
|
|
|
std::find(currentThreads.begin(), currentThreads.end(), tid);
|
2009-02-11 00:49:29 +01:00
|
|
|
|
|
|
|
return (isCurrent != currentThreads.end());
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::addToCurrentThreads(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
if (!isThreadInCPU(tid)) {
|
|
|
|
DPRINTF(InOrderCPU, "Adding Thread %i to current threads list in CPU.\n",
|
|
|
|
tid);
|
|
|
|
currentThreads.push_back(tid);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::removeFromCurrentThreads(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
if (isThreadInCPU(tid)) {
|
2009-05-26 18:23:13 +02:00
|
|
|
DPRINTF(InOrderCPU,
|
|
|
|
"Adding Thread %i to current threads list in CPU.\n", tid);
|
|
|
|
list<ThreadID>::iterator isCurrent =
|
|
|
|
std::find(currentThreads.begin(), currentThreads.end(), tid);
|
2009-02-11 00:49:29 +01:00
|
|
|
currentThreads.erase(isCurrent);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::isThreadSuspended(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
2009-05-26 18:23:13 +02:00
|
|
|
list<ThreadID>::iterator isSuspended =
|
|
|
|
std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
|
2009-02-11 00:49:29 +01:00
|
|
|
|
|
|
|
return (isSuspended!= suspendedThreads.end());
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::enableVirtProcElement(unsigned vpe)
|
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU, "[vpe:%i]: Scheduling "
|
|
|
|
"Enabling of concurrent virtual processor execution",
|
|
|
|
vpe);
|
|
|
|
|
|
|
|
scheduleCpuEvent(EnableVPEs, NoFault, 0/*tid*/, vpe);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::enableVPEs(unsigned vpe)
|
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU, "[vpe:%i]: Enabling Concurrent Execution "
|
|
|
|
"virtual processors %i", vpe);
|
|
|
|
|
2009-05-26 18:23:13 +02:00
|
|
|
list<ThreadID>::iterator thread_it = currentThreads.begin();
|
2009-02-11 00:49:29 +01:00
|
|
|
|
|
|
|
while (thread_it != currentThreads.end()) {
|
|
|
|
if (!isThreadSuspended(*thread_it)) {
|
|
|
|
activateThread(*thread_it);
|
|
|
|
}
|
|
|
|
thread_it++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::disableVirtProcElement(ThreadID tid, unsigned vpe)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU, "[vpe:%i]: Scheduling "
|
|
|
|
"Disabling of concurrent virtual processor execution",
|
|
|
|
vpe);
|
|
|
|
|
|
|
|
scheduleCpuEvent(DisableVPEs, NoFault, 0/*tid*/, vpe);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::disableVPEs(ThreadID tid, unsigned vpe)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU, "[vpe:%i]: Disabling Concurrent Execution of "
|
|
|
|
"virtual processors %i", vpe);
|
|
|
|
|
|
|
|
unsigned base_vpe = TheISA::getVirtProcNum(tcBase(tid));
|
|
|
|
|
2009-05-26 18:23:13 +02:00
|
|
|
list<ThreadID>::iterator thread_it = activeThreads.begin();
|
2009-02-11 00:49:29 +01:00
|
|
|
|
2009-05-26 18:23:13 +02:00
|
|
|
vector<list<ThreadID>::iterator> removeList;
|
2009-02-11 00:49:29 +01:00
|
|
|
|
|
|
|
while (thread_it != activeThreads.end()) {
|
|
|
|
if (base_vpe != vpe) {
|
|
|
|
removeList.push_back(thread_it);
|
|
|
|
}
|
|
|
|
thread_it++;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (int i = 0; i < removeList.size(); i++) {
|
|
|
|
activeThreads.erase(removeList[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::enableMultiThreading(unsigned vpe)
|
|
|
|
{
|
|
|
|
// Schedule event to take place at end of cycle
|
|
|
|
DPRINTF(InOrderCPU, "[vpe:%i]: Scheduling Enable Multithreading on "
|
|
|
|
"virtual processor %i", vpe);
|
|
|
|
|
|
|
|
scheduleCpuEvent(EnableThreads, NoFault, 0/*tid*/, vpe);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::enableThreads(unsigned vpe)
|
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU, "[vpe:%i]: Enabling Multithreading on "
|
|
|
|
"virtual processor %i", vpe);
|
|
|
|
|
2009-05-26 18:23:13 +02:00
|
|
|
list<ThreadID>::iterator thread_it = currentThreads.begin();
|
2009-02-11 00:49:29 +01:00
|
|
|
|
|
|
|
while (thread_it != currentThreads.end()) {
|
|
|
|
if (TheISA::getVirtProcNum(tcBase(*thread_it)) == vpe) {
|
|
|
|
if (!isThreadSuspended(*thread_it)) {
|
|
|
|
activateThread(*thread_it);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
thread_it++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::disableMultiThreading(ThreadID tid, unsigned vpe)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
// Schedule event to take place at end of cycle
|
|
|
|
DPRINTF(InOrderCPU, "[tid:%i]: Scheduling Disable Multithreading on "
|
|
|
|
"virtual processor %i", tid, vpe);
|
|
|
|
|
|
|
|
scheduleCpuEvent(DisableThreads, NoFault, tid, vpe);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::disableThreads(ThreadID tid, unsigned vpe)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU, "[tid:%i]: Disabling Multithreading on "
|
|
|
|
"virtual processor %i", tid, vpe);
|
|
|
|
|
2009-05-26 18:23:13 +02:00
|
|
|
list<ThreadID>::iterator thread_it = activeThreads.begin();
|
2009-02-11 00:49:29 +01:00
|
|
|
|
2009-05-26 18:23:13 +02:00
|
|
|
vector<list<ThreadID>::iterator> removeList;
|
2009-02-11 00:49:29 +01:00
|
|
|
|
|
|
|
while (thread_it != activeThreads.end()) {
|
|
|
|
if (TheISA::getVirtProcNum(tcBase(*thread_it)) == vpe) {
|
|
|
|
removeList.push_back(thread_it);
|
|
|
|
}
|
|
|
|
thread_it++;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (int i = 0; i < removeList.size(); i++) {
|
|
|
|
activeThreads.erase(removeList[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::updateThreadPriority()
|
|
|
|
{
|
|
|
|
if (activeThreads.size() > 1)
|
|
|
|
{
|
|
|
|
//DEFAULT TO ROUND ROBIN SCHEME
|
|
|
|
//e.g. Move highest priority to end of thread list
|
2009-05-26 18:23:13 +02:00
|
|
|
list<ThreadID>::iterator list_begin = activeThreads.begin();
|
|
|
|
list<ThreadID>::iterator list_end = activeThreads.end();
|
2009-02-11 00:49:29 +01:00
|
|
|
|
|
|
|
unsigned high_thread = *list_begin;
|
|
|
|
|
|
|
|
activeThreads.erase(list_begin);
|
|
|
|
|
|
|
|
activeThreads.push_back(high_thread);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
inline void
|
|
|
|
InOrderCPU::tickThreadStats()
|
|
|
|
{
|
|
|
|
/** Keep track of cycles that each thread is active */
|
2009-05-26 18:23:13 +02:00
|
|
|
list<ThreadID>::iterator thread_it = activeThreads.begin();
|
2009-02-11 00:49:29 +01:00
|
|
|
while (thread_it != activeThreads.end()) {
|
|
|
|
threadCycles[*thread_it]++;
|
|
|
|
thread_it++;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Keep track of cycles where SMT is active
|
|
|
|
if (activeThreads.size() > 1) {
|
|
|
|
smtCycles++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::activateContext(ThreadID tid, int delay)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
|
|
|
|
|
|
|
|
scheduleCpuEvent(ActivateThread, NoFault, tid, 0/*vpe*/, delay);
|
|
|
|
|
|
|
|
// Be sure to signal that there's some activity so the CPU doesn't
|
|
|
|
// deschedule itself.
|
|
|
|
activityRec.activity();
|
|
|
|
|
|
|
|
_status = Running;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::suspendContext(ThreadID tid, int delay)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
scheduleCpuEvent(SuspendThread, NoFault, tid, 0/*vpe*/, delay);
|
|
|
|
//_status = Idle;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::suspendThread(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU,"[tid: %i]: Suspended ...\n", tid);
|
|
|
|
deactivateThread(tid);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::deallocateContext(ThreadID tid, int delay)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
scheduleCpuEvent(DeallocateThread, NoFault, tid, 0/*vpe*/, delay);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::deallocateThread(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU,"[tid:%i]: Deallocating ...", tid);
|
|
|
|
|
|
|
|
removeFromCurrentThreads(tid);
|
|
|
|
|
|
|
|
deactivateThread(tid);
|
|
|
|
|
|
|
|
squashThreadInPipeline(tid);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::squashThreadInPipeline(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
//Squash all instructions in each stage
|
|
|
|
for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
|
|
|
|
pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::haltContext(ThreadID tid, int delay)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU, "[tid:%i]: Halt context called.\n", tid);
|
|
|
|
|
|
|
|
// Halt is same thing as deallocate for now
|
|
|
|
// @TODO: Differentiate between halt & deallocate in the CPU
|
|
|
|
// model
|
|
|
|
deallocateContext(tid, delay);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::insertThread(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
panic("Unimplemented Function\n.");
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::removeThread(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU, "Removing Thread %i from CPU.\n", tid);
|
|
|
|
|
|
|
|
/** Broadcast to CPU resources*/
|
|
|
|
}
|
|
|
|
|
2009-05-12 21:01:13 +02:00
|
|
|
PipelineStage*
|
|
|
|
InOrderCPU::getPipeStage(int stage_num)
|
|
|
|
{
|
|
|
|
return pipelineStage[stage_num];
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-02-11 00:49:29 +01:00
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::activateWhenReady(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
panic("Unimplemented Function\n.");
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
uint64_t
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::readPC(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
return PC[tid];
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::setPC(Addr new_PC, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
PC[tid] = new_PC;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
uint64_t
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::readNextPC(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
return nextPC[tid];
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::setNextPC(uint64_t new_NPC, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
nextPC[tid] = new_NPC;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
uint64_t
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::readNextNPC(ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
return nextNPC[tid];
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::setNextNPC(uint64_t new_NNPC, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
nextNPC[tid] = new_NNPC;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
return intRegFile[tid].readReg(reg_idx);
|
|
|
|
}
|
|
|
|
|
|
|
|
FloatReg
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::readFloatReg(int reg_idx, ThreadID tid, int width)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
|
|
|
|
return floatRegFile[tid].readReg(reg_idx, width);
|
|
|
|
}
|
|
|
|
|
|
|
|
FloatRegBits
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid, int width)
|
2009-02-11 00:49:29 +01:00
|
|
|
{;
|
|
|
|
return floatRegFile[tid].readRegBits(reg_idx, width);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
intRegFile[tid].setReg(reg_idx, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid, int width)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
floatRegFile[tid].setReg(reg_idx, val, width);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid,
|
|
|
|
int width)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
floatRegFile[tid].setRegBits(reg_idx, val, width);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
// If Default value is set, then retrieve target thread
|
2009-05-26 18:23:13 +02:00
|
|
|
if (tid == InvalidThreadID) {
|
2009-02-11 00:49:29 +01:00
|
|
|
tid = TheISA::getTargetThread(tcBase(tid));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg_idx < FP_Base_DepTag) { // Integer Register File
|
|
|
|
return readIntReg(reg_idx, tid);
|
|
|
|
} else if (reg_idx < Ctrl_Base_DepTag) { // Float Register File
|
|
|
|
reg_idx -= FP_Base_DepTag;
|
|
|
|
return readFloatRegBits(reg_idx, tid);
|
|
|
|
} else {
|
|
|
|
reg_idx -= Ctrl_Base_DepTag;
|
|
|
|
return readMiscReg(reg_idx, tid); // Misc. Register File
|
|
|
|
}
|
|
|
|
}
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
|
|
|
|
ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
// If Default value is set, then retrieve target thread
|
2009-05-26 18:23:13 +02:00
|
|
|
if (tid == InvalidThreadID) {
|
2009-02-11 00:49:29 +01:00
|
|
|
tid = TheISA::getTargetThread(tcBase(tid));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg_idx < FP_Base_DepTag) { // Integer Register File
|
|
|
|
setIntReg(reg_idx, val, tid);
|
|
|
|
} else if (reg_idx < Ctrl_Base_DepTag) { // Float Register File
|
|
|
|
reg_idx -= FP_Base_DepTag;
|
|
|
|
setFloatRegBits(reg_idx, val, tid);
|
|
|
|
} else {
|
|
|
|
reg_idx -= Ctrl_Base_DepTag;
|
|
|
|
setMiscReg(reg_idx, val, tid); // Misc. Register File
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
MiscReg
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
return miscRegFile.readRegNoEffect(misc_reg, tid);
|
|
|
|
}
|
|
|
|
|
|
|
|
MiscReg
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
return miscRegFile.readReg(misc_reg, tcBase(tid), tid);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
miscRegFile.setRegNoEffect(misc_reg, val, tid);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
miscRegFile.setReg(misc_reg, val, tcBase(tid), tid);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
InOrderCPU::ListIt
|
|
|
|
InOrderCPU::addInst(DynInstPtr &inst)
|
|
|
|
{
|
2009-05-26 18:23:13 +02:00
|
|
|
ThreadID tid = inst->readTid();
|
2009-02-11 00:49:29 +01:00
|
|
|
|
|
|
|
instList[tid].push_back(inst);
|
|
|
|
|
|
|
|
return --(instList[tid].end());
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
// Set the CPU's PCs - This contributes to the precise state of the CPU which can be used
|
|
|
|
// when restoring a thread to the CPU after a fork or after an exception
|
|
|
|
// @TODO: Set-Up Grad-Info/Committed-Info to let ThreadState know if it's a branch or not
|
|
|
|
setPC(inst->readPC(), tid);
|
|
|
|
setNextPC(inst->readNextPC(), tid);
|
|
|
|
setNextNPC(inst->readNextNPC(), tid);
|
|
|
|
|
|
|
|
// Finalize Trace Data For Instruction
|
|
|
|
if (inst->traceData) {
|
|
|
|
//inst->traceData->setCycle(curTick);
|
|
|
|
inst->traceData->setFetchSeq(inst->seqNum);
|
|
|
|
//inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
|
|
|
|
inst->traceData->dump();
|
|
|
|
delete inst->traceData;
|
|
|
|
inst->traceData = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Set Last Graduated Instruction In Thread State
|
|
|
|
//thread[tid]->lastGradInst = inst;
|
|
|
|
|
|
|
|
// Increment thread-state's instruction count
|
|
|
|
thread[tid]->numInst++;
|
|
|
|
|
|
|
|
// Increment thread-state's instruction stats
|
|
|
|
thread[tid]->numInsts++;
|
|
|
|
|
|
|
|
// Count committed insts per thread stats
|
|
|
|
committedInsts[tid]++;
|
|
|
|
|
|
|
|
// Count total insts committed stat
|
|
|
|
totalCommittedInsts++;
|
|
|
|
|
|
|
|
// Count SMT-committed insts per thread stat
|
|
|
|
if (numActiveThreads() > 1) {
|
|
|
|
smtCommittedInsts[tid]++;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Check for instruction-count-based events.
|
|
|
|
comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
|
|
|
|
|
|
|
|
// Broadcast to other resources an instruction
|
|
|
|
// has been completed
|
|
|
|
resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst, tid);
|
|
|
|
|
|
|
|
// Finally, remove instruction from CPU
|
|
|
|
removeInst(inst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::addToRemoveList(DynInstPtr &inst)
|
|
|
|
{
|
|
|
|
removeInstsThisCycle = true;
|
|
|
|
|
|
|
|
removeList.push(inst->getInstListIt());
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::removeInst(DynInstPtr &inst)
|
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %#x "
|
|
|
|
"[sn:%lli]\n",
|
|
|
|
inst->threadNumber, inst->readPC(), inst->seqNum);
|
|
|
|
|
|
|
|
removeInstsThisCycle = true;
|
|
|
|
|
|
|
|
// Remove the instruction.
|
|
|
|
removeList.push(inst->getInstListIt());
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
//assert(!instList[tid].empty());
|
|
|
|
|
|
|
|
removeInstsThisCycle = true;
|
|
|
|
|
|
|
|
ListIt inst_iter = instList[tid].end();
|
|
|
|
|
|
|
|
inst_iter--;
|
|
|
|
|
|
|
|
DPRINTF(InOrderCPU, "Deleting instructions from CPU instruction "
|
|
|
|
"list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
|
|
|
|
tid, seq_num, (*inst_iter)->seqNum);
|
|
|
|
|
|
|
|
while ((*inst_iter)->seqNum > seq_num) {
|
|
|
|
|
|
|
|
bool break_loop = (inst_iter == instList[tid].begin());
|
|
|
|
|
|
|
|
squashInstIt(inst_iter, tid);
|
|
|
|
|
|
|
|
inst_iter--;
|
|
|
|
|
|
|
|
if (break_loop)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
inline void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
if ((*instIt)->threadNumber == tid) {
|
|
|
|
DPRINTF(InOrderCPU, "Squashing instruction, "
|
|
|
|
"[tid:%i] [sn:%lli] PC %#x\n",
|
|
|
|
(*instIt)->threadNumber,
|
|
|
|
(*instIt)->seqNum,
|
|
|
|
(*instIt)->readPC());
|
|
|
|
|
|
|
|
(*instIt)->setSquashed();
|
|
|
|
|
|
|
|
removeList.push(instIt);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::cleanUpRemovedInsts()
|
|
|
|
{
|
|
|
|
while (!removeList.empty()) {
|
|
|
|
DPRINTF(InOrderCPU, "Removing instruction, "
|
|
|
|
"[tid:%i] [sn:%lli] PC %#x\n",
|
|
|
|
(*removeList.front())->threadNumber,
|
|
|
|
(*removeList.front())->seqNum,
|
|
|
|
(*removeList.front())->readPC());
|
|
|
|
|
|
|
|
DynInstPtr inst = *removeList.front();
|
2009-05-26 18:23:13 +02:00
|
|
|
ThreadID tid = inst->threadNumber;
|
2009-02-11 00:49:29 +01:00
|
|
|
|
|
|
|
// Make Sure Resource Schedule Is Emptied Out
|
|
|
|
ThePipeline::ResSchedule *inst_sched = &inst->resSched;
|
|
|
|
while (!inst_sched->empty()) {
|
|
|
|
ThePipeline::ScheduleEntry* sch_entry = inst_sched->top();
|
|
|
|
inst_sched->pop();
|
|
|
|
delete sch_entry;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Remove From Register Dependency Map, If Necessary
|
|
|
|
archRegDepMap[(*removeList.front())->threadNumber].
|
|
|
|
remove((*removeList.front()));
|
|
|
|
|
|
|
|
|
|
|
|
// Clear if Non-Speculative
|
|
|
|
if (inst->staticInst &&
|
|
|
|
inst->seqNum == nonSpecSeqNum[tid] &&
|
|
|
|
nonSpecInstActive[tid] == true) {
|
|
|
|
nonSpecInstActive[tid] = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
instList[tid].erase(removeList.front());
|
|
|
|
|
|
|
|
removeList.pop();
|
|
|
|
|
|
|
|
DPRINTF(RefCount, "pop from remove list: [sn:%i]: Refcount = %i.\n",
|
|
|
|
inst->seqNum,
|
|
|
|
0/*inst->curCount()*/);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
removeInstsThisCycle = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::cleanUpRemovedReqs()
|
|
|
|
{
|
|
|
|
while (!reqRemoveList.empty()) {
|
|
|
|
ResourceRequest *res_req = reqRemoveList.front();
|
|
|
|
|
|
|
|
DPRINTF(RefCount, "[tid:%i]: Removing Request, "
|
|
|
|
"[sn:%lli] [slot:%i] [stage_num:%i] [res:%s] [refcount:%i].\n",
|
|
|
|
res_req->inst->threadNumber,
|
|
|
|
res_req->inst->seqNum,
|
|
|
|
res_req->getSlot(),
|
|
|
|
res_req->getStageNum(),
|
|
|
|
res_req->res->name(),
|
|
|
|
0/*res_req->inst->curCount()*/);
|
|
|
|
|
|
|
|
reqRemoveList.pop();
|
|
|
|
|
|
|
|
delete res_req;
|
|
|
|
|
|
|
|
DPRINTF(RefCount, "after remove request: [sn:%i]: Refcount = %i.\n",
|
|
|
|
res_req->inst->seqNum,
|
|
|
|
0/*res_req->inst->curCount()*/);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::cleanUpRemovedEvents()
|
|
|
|
{
|
|
|
|
while (!cpuEventRemoveList.empty()) {
|
|
|
|
Event *cpu_event = cpuEventRemoveList.front();
|
|
|
|
cpuEventRemoveList.pop();
|
|
|
|
delete cpu_event;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::dumpInsts()
|
|
|
|
{
|
|
|
|
int num = 0;
|
|
|
|
|
|
|
|
ListIt inst_list_it = instList[0].begin();
|
|
|
|
|
|
|
|
cprintf("Dumping Instruction List\n");
|
|
|
|
|
|
|
|
while (inst_list_it != instList[0].end()) {
|
|
|
|
cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
|
|
|
|
"Squashed:%i\n\n",
|
|
|
|
num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
|
|
|
|
(*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
|
|
|
|
(*inst_list_it)->isSquashed());
|
|
|
|
inst_list_it++;
|
|
|
|
++num;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::wakeCPU()
|
|
|
|
{
|
|
|
|
if (/*activityRec.active() || */tickEvent.scheduled()) {
|
|
|
|
DPRINTF(Activity, "CPU already running.\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
DPRINTF(Activity, "Waking up CPU\n");
|
|
|
|
|
2009-03-04 19:17:08 +01:00
|
|
|
//@todo: figure out how to count idleCycles correctly
|
2009-02-11 00:49:29 +01:00
|
|
|
//idleCycles += (curTick - 1) - lastRunningCycle;
|
|
|
|
|
|
|
|
mainEventQueue.schedule(&tickEvent, curTick);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-05-26 18:23:13 +02:00
|
|
|
InOrderCPU::syscall(int64_t callnum, ThreadID tid)
|
2009-02-11 00:49:29 +01:00
|
|
|
{
|
|
|
|
DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
|
|
|
|
|
|
|
|
DPRINTF(Activity,"Activity: syscall() called.\n");
|
|
|
|
|
|
|
|
// Temporarily increase this by one to account for the syscall
|
|
|
|
// instruction.
|
|
|
|
++(this->thread[tid]->funcExeInst);
|
|
|
|
|
|
|
|
// Execute the actual syscall.
|
|
|
|
this->thread[tid]->syscall(callnum);
|
|
|
|
|
|
|
|
// Decrease funcExeInst by one as the normal commit will handle
|
|
|
|
// incrementing it.
|
|
|
|
--(this->thread[tid]->funcExeInst);
|
|
|
|
|
|
|
|
// Clear Non-Speculative Block Variable
|
|
|
|
nonSpecInstActive[tid] = false;
|
|
|
|
}
|
|
|
|
|
2009-05-12 21:01:15 +02:00
|
|
|
void
|
|
|
|
InOrderCPU::prefetch(DynInstPtr inst)
|
|
|
|
{
|
|
|
|
Resource *mem_res = resPool->getResource(dataPortIdx);
|
|
|
|
return mem_res->prefetch(inst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
InOrderCPU::writeHint(DynInstPtr inst)
|
|
|
|
{
|
|
|
|
Resource *mem_res = resPool->getResource(dataPortIdx);
|
|
|
|
return mem_res->writeHint(inst);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-05-12 21:01:14 +02:00
|
|
|
TheISA::TLB*
|
2009-05-12 21:01:13 +02:00
|
|
|
InOrderCPU::getITBPtr()
|
|
|
|
{
|
2009-05-12 21:01:16 +02:00
|
|
|
CacheUnit *itb_res =
|
|
|
|
dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
|
2009-05-12 21:01:14 +02:00
|
|
|
return itb_res->tlb();
|
2009-05-12 21:01:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-05-12 21:01:14 +02:00
|
|
|
TheISA::TLB*
|
2009-05-12 21:01:13 +02:00
|
|
|
InOrderCPU::getDTBPtr()
|
|
|
|
{
|
2009-05-12 21:01:16 +02:00
|
|
|
CacheUnit *dtb_res =
|
|
|
|
dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
|
2009-05-12 21:01:14 +02:00
|
|
|
return dtb_res->tlb();
|
2009-05-12 21:01:13 +02:00
|
|
|
}
|
2009-05-12 21:01:16 +02:00
|
|
|
|
|
|
|
template <class T>
|
|
|
|
Fault
|
|
|
|
InOrderCPU::read(DynInstPtr inst, Addr addr, T &data, unsigned flags)
|
|
|
|
{
|
|
|
|
//@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
|
|
|
|
// you want to run w/out caches?
|
|
|
|
CacheUnit *cache_res = dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
|
|
|
|
|
|
|
|
return cache_res->read(inst, addr, data, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
InOrderCPU::read(DynInstPtr inst, Addr addr, Twin32_t &data, unsigned flags);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
InOrderCPU::read(DynInstPtr inst, Addr addr, Twin64_t &data, unsigned flags);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
InOrderCPU::read(DynInstPtr inst, Addr addr, uint64_t &data, unsigned flags);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
InOrderCPU::read(DynInstPtr inst, Addr addr, uint32_t &data, unsigned flags);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
InOrderCPU::read(DynInstPtr inst, Addr addr, uint16_t &data, unsigned flags);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
InOrderCPU::read(DynInstPtr inst, Addr addr, uint8_t &data, unsigned flags);
|
|
|
|
|
|
|
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
|
|
|
|
template<>
|
|
|
|
Fault
|
|
|
|
InOrderCPU::read(DynInstPtr inst, Addr addr, double &data, unsigned flags)
|
|
|
|
{
|
|
|
|
return read(inst, addr, *(uint64_t*)&data, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
template<>
|
|
|
|
Fault
|
|
|
|
InOrderCPU::read(DynInstPtr inst, Addr addr, float &data, unsigned flags)
|
|
|
|
{
|
|
|
|
return read(inst, addr, *(uint32_t*)&data, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
template<>
|
|
|
|
Fault
|
|
|
|
InOrderCPU::read(DynInstPtr inst, Addr addr, int32_t &data, unsigned flags)
|
|
|
|
{
|
|
|
|
return read(inst, addr, (uint32_t&)data, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
template <class T>
|
|
|
|
Fault
|
|
|
|
InOrderCPU::write(DynInstPtr inst, T data, Addr addr, unsigned flags,
|
|
|
|
uint64_t *write_res)
|
|
|
|
{
|
|
|
|
//@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
|
|
|
|
// you want to run w/out caches?
|
|
|
|
CacheUnit *cache_res =
|
|
|
|
dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
|
|
|
|
return cache_res->write(inst, data, addr, flags, write_res);
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
InOrderCPU::write(DynInstPtr inst, Twin32_t data, Addr addr,
|
|
|
|
unsigned flags, uint64_t *res);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
InOrderCPU::write(DynInstPtr inst, Twin64_t data, Addr addr,
|
|
|
|
unsigned flags, uint64_t *res);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
InOrderCPU::write(DynInstPtr inst, uint64_t data, Addr addr,
|
|
|
|
unsigned flags, uint64_t *res);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
InOrderCPU::write(DynInstPtr inst, uint32_t data, Addr addr,
|
|
|
|
unsigned flags, uint64_t *res);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
InOrderCPU::write(DynInstPtr inst, uint16_t data, Addr addr,
|
|
|
|
unsigned flags, uint64_t *res);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
InOrderCPU::write(DynInstPtr inst, uint8_t data, Addr addr,
|
|
|
|
unsigned flags, uint64_t *res);
|
|
|
|
|
|
|
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
|
|
|
|
template<>
|
|
|
|
Fault
|
|
|
|
InOrderCPU::write(DynInstPtr inst, double data, Addr addr, unsigned flags, uint64_t *res)
|
|
|
|
{
|
|
|
|
return write(inst, *(uint64_t*)&data, addr, flags, res);
|
|
|
|
}
|
|
|
|
|
|
|
|
template<>
|
|
|
|
Fault
|
|
|
|
InOrderCPU::write(DynInstPtr inst, float data, Addr addr, unsigned flags, uint64_t *res)
|
|
|
|
{
|
|
|
|
return write(inst, *(uint32_t*)&data, addr, flags, res);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
template<>
|
|
|
|
Fault
|
|
|
|
InOrderCPU::write(DynInstPtr inst, int32_t data, Addr addr, unsigned flags, uint64_t *res)
|
|
|
|
{
|
|
|
|
return write(inst, (uint32_t)data, addr, flags, res);
|
|
|
|
}
|