2010-06-02 19:58:00 +02:00
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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2009-06-22 02:21:25 +02:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#include "arch/arm/insts/pred_inst.hh"
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namespace ArmISA
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{
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std::string
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2009-07-09 08:02:19 +02:00
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PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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2009-06-22 02:21:25 +02:00
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{
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std::stringstream ss;
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2010-06-02 19:58:02 +02:00
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unsigned rotate = machInst.rotate * 2;
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uint32_t imm = machInst.imm;
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imm = (imm << (32 - rotate)) | (imm >> rotate);
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printDataInst(ss, false, machInst.opcode4 == 0, machInst.sField,
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(IntRegIndex)(uint32_t)machInst.rd,
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(IntRegIndex)(uint32_t)machInst.rn,
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(IntRegIndex)(uint32_t)machInst.rm,
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(IntRegIndex)(uint32_t)machInst.rs,
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machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift,
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imm);
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2009-07-09 08:02:19 +02:00
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return ss.str();
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}
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std::string
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2010-06-02 19:58:02 +02:00
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PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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2009-07-09 08:02:19 +02:00
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{
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std::stringstream ss;
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2010-06-02 19:58:02 +02:00
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printDataInst(ss, true, machInst.opcode4 == 0, machInst.sField,
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(IntRegIndex)(uint32_t)machInst.rd,
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(IntRegIndex)(uint32_t)machInst.rn,
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(IntRegIndex)(uint32_t)machInst.rm,
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(IntRegIndex)(uint32_t)machInst.rs,
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machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift,
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imm);
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return ss.str();
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}
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std::string
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DataImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1,
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INTREG_ZERO, INTREG_ZERO, 0, LSL, imm);
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return ss.str();
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}
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std::string
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DataRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
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op2, INTREG_ZERO, shiftAmt, shiftType, 0);
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return ss.str();
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}
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std::string
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DataRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printDataInst(ss, false, false, /*XXX not really s*/ false, dest, op1,
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op2, shift, 0, shiftType, 0);
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2009-06-22 02:21:25 +02:00
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return ss.str();
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}
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std::string
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PredMacroOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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return ss.str();
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}
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}
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