gem5/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr

warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here
inorder-regress: add twolf ALPHA-SE 2009-05-12 21:01:16 +02:00			`warn: Sockets disabled, not accepting gdb connections`
			`For more information see: http://www.m5sim.org/warn/d946bea6`
imported patch regression_updates 2011-02-04 06:09:22 +01:00			`warn: Prefetch instrutions is Alpha do not do anything`
			`For more information see: http://www.m5sim.org/warn/3e0eccba`
			`warn: Prefetch instrutions is Alpha do not do anything`
			`For more information see: http://www.m5sim.org/warn/3e0eccba`
			`warn: Prefetch instrutions is Alpha do not do anything`
			`For more information see: http://www.m5sim.org/warn/3e0eccba`
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU. 2010-09-09 20:40:19 +02:00			`warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)`
			`For more information see: http://www.m5sim.org/warn/5c5b547f`
			`hack: be nice to actually delete the event here`