gem5/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                 227392                       # Simulator instruction rate (inst/s)
host_mem_usage                                 190044                       # Number of bytes of host memory used
host_seconds                                     0.07                       # Real time elapsed on the host
host_tick_rate                              637540839                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                       15175                       # Number of instructions simulated
sim_seconds                                  0.000043                       # Number of seconds simulated
sim_ticks                                    42735000                       # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses               2226                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits                   2173                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency        2968000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.023810                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                   53                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency      2809000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.023810                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses              53                       # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses                  6                       # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_hits                      6                       # number of SwapReq hits
system.cpu.dcache.WriteReq_accesses              1442                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits                  1340                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency       5712000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.070735                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses                 102                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency      5406000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.070735                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses            102                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                  25.623188                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses                3668                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency        56000                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                    3513                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency         8680000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.042257                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                   155                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency      8215000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.042257                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses              155                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0                   0.023864                       # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0             97.747327                       # Average occupied blocks per context
system.cpu.dcache.overall_accesses               3668                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits                   3513                       # number of overall hits
system.cpu.dcache.overall_miss_latency        8680000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.042257                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                  155                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency      8215000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.042257                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses             155                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse                 97.747327                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     3536                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                        0                       # number of writebacks
system.cpu.icache.ReadReq_accesses              15221                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency        55700                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency        52700                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits                  14941                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency       15596000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.018396                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                  280                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency     14756000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.018396                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             280                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                  53.360714                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses               15221                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency        55700                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency        52700                       # average overall mshr miss latency
system.cpu.icache.demand_hits                   14941                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency        15596000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.018396                       # miss rate for demand accesses
system.cpu.icache.demand_misses                   280                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency     14756000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.018396                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              280                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_%::0                   0.074743                       # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0            153.073222                       # Average occupied blocks per context
system.cpu.icache.overall_accesses              15221                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency        55700                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency        52700                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits                  14941                       # number of overall hits
system.cpu.icache.overall_miss_latency       15596000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.018396                       # miss rate for overall accesses
system.cpu.icache.overall_misses                  280                       # number of overall misses
system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency     14756000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.018396                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses             280                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                      0                       # number of replacements
system.cpu.icache.sampled_refs                    280                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                153.073222                       # Cycle average of tags in use
system.cpu.icache.total_refs                    14941                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses              85                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency      4420000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses                85                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency      3400000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses           85                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses               333                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency      17212000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.993994                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                 331                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency     13240000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.993994                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses            331                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses             17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency       884000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses               17                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency       680000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses           17                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.006369                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses                418                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency       21632000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.995215                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses                  416                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency     16640000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.995215                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses             416                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0                  0.005323                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0           174.433606                       # Average occupied blocks per context
system.cpu.l2cache.overall_accesses               418                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                     2                       # number of overall hits
system.cpu.l2cache.overall_miss_latency      21632000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.995215                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses                 416                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency     16640000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.995215                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses            416                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.sampled_refs                   314                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse               174.433606                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.numCycles                            85470                       # number of cpu cycles simulated
system.cpu.num_insts                            15175                       # Number of instructions executed
system.cpu.num_refs                              3684                       # Number of memory references
system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls

---------- End Simulation Statistics   ----------