2013-06-27 11:49:50 +02:00
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# Copyright (c) 2012-2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Prakash Ramrakhyani
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from m5.params import *
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from m5.proxy import *
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from ClockedObject import ClockedObject
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class BaseTags(ClockedObject):
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type = 'BaseTags'
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abstract = True
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cxx_header = "mem/cache/tags/base.hh"
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# Get the size from the parent (cache)
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size = Param.MemorySize(Parent.size, "capacity in bytes")
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2013-07-18 14:31:16 +02:00
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# Get the block size from the parent (system)
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block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
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2013-06-27 11:49:50 +02:00
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2016-11-30 23:10:27 +01:00
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# Get the tag lookup latency from the parent (cache)
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tag_latency = Param.Cycles(Parent.tag_latency,
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"The tag lookup latency for this cache")
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# Get the RAM access latency from the parent (cache)
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data_latency = Param.Cycles(Parent.data_latency,
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"The data access latency for this cache")
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sequential_access = Param.Bool(Parent.sequential_access,
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"Whether to access tags and data sequentially")
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2013-06-27 11:49:50 +02:00
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2014-07-28 18:23:23 +02:00
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class BaseSetAssoc(BaseTags):
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type = 'BaseSetAssoc'
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abstract = True
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cxx_header = "mem/cache/tags/base_set_assoc.hh"
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2013-06-27 11:49:50 +02:00
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assoc = Param.Int(Parent.assoc, "associativity")
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2014-07-28 18:23:23 +02:00
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class LRU(BaseSetAssoc):
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type = 'LRU'
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cxx_class = 'LRU'
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cxx_header = "mem/cache/tags/lru.hh"
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class RandomRepl(BaseSetAssoc):
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type = 'RandomRepl'
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cxx_class = 'RandomRepl'
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cxx_header = "mem/cache/tags/random_repl.hh"
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2013-06-27 11:49:50 +02:00
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class FALRU(BaseTags):
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type = 'FALRU'
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cxx_class = 'FALRU'
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cxx_header = "mem/cache/tags/fa_lru.hh"
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