660 lines
76 KiB
Text
660 lines
76 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000796 # Number of seconds simulated
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sim_ticks 796036 # Number of ticks simulated
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final_tick 796036 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000 # Frequency of simulated ticks
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host_inst_rate 51863 # Simulator instruction rate (inst/s)
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host_op_rate 51862 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 623875 # Simulator tick rate (ticks/s)
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host_mem_usage 411084 # Number of bytes of host memory used
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host_seconds 1.28 # Real time elapsed on the host
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sim_insts 66173 # Number of instructions simulated
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sim_ops 66173 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1 # Clock period in ticks
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system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
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system.mem_ctrls.bytes_read::ruby.dir_cntrl0 899200 # Number of bytes read from this memory
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system.mem_ctrls.bytes_read::total 899200 # Number of bytes read from this memory
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system.mem_ctrls.bytes_written::ruby.dir_cntrl0 898944 # Number of bytes written to this memory
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system.mem_ctrls.bytes_written::total 898944 # Number of bytes written to this memory
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system.mem_ctrls.num_reads::ruby.dir_cntrl0 14050 # Number of read requests responded to by this memory
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system.mem_ctrls.num_reads::total 14050 # Number of read requests responded to by this memory
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system.mem_ctrls.num_writes::ruby.dir_cntrl0 14046 # Number of write requests responded to by this memory
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system.mem_ctrls.num_writes::total 14046 # Number of write requests responded to by this memory
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system.mem_ctrls.bw_read::ruby.dir_cntrl0 1129597154 # Total read bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_read::total 1129597154 # Total read bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_write::ruby.dir_cntrl0 1129275560 # Write bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_write::total 1129275560 # Write bandwidth from this memory (bytes/s)
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system.mem_ctrls.bw_total::ruby.dir_cntrl0 2258872714 # Total bandwidth to/from this memory (bytes/s)
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system.mem_ctrls.bw_total::total 2258872714 # Total bandwidth to/from this memory (bytes/s)
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system.mem_ctrls.readReqs 14050 # Number of read requests accepted
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system.mem_ctrls.writeReqs 14046 # Number of write requests accepted
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system.mem_ctrls.readBursts 14050 # Number of DRAM read bursts, including those serviced by the write queue
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system.mem_ctrls.writeBursts 14046 # Number of DRAM write bursts, including those merged in the write queue
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system.mem_ctrls.bytesReadDRAM 236096 # Total number of bytes read from DRAM
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system.mem_ctrls.bytesReadWrQ 663104 # Total number of bytes read from write queue
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system.mem_ctrls.bytesWritten 245056 # Total number of bytes written to DRAM
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system.mem_ctrls.bytesReadSys 899200 # Total read bytes from the system interface side
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system.mem_ctrls.bytesWrittenSys 898944 # Total written bytes from the system interface side
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system.mem_ctrls.servicedByWrQ 10361 # Number of DRAM read bursts serviced by the write queue
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system.mem_ctrls.mergedWrBursts 10190 # Number of DRAM write bursts merged with an existing one
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system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.mem_ctrls.perBankRdBursts::0 171 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::1 11 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::2 5 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::3 94 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::4 190 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::5 318 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::6 159 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::7 59 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::8 94 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::9 356 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::10 241 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::11 240 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::12 629 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::13 494 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::14 606 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::15 22 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::0 175 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::1 12 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::2 4 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::3 95 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::4 197 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::5 332 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::6 163 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::7 63 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::8 96 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::9 353 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::10 243 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::11 245 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::12 639 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::13 514 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::14 676 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::15 22 # Per bank write bursts
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system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
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system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
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system.mem_ctrls.totGap 795950 # Total gap between requests
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system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
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system.mem_ctrls.readPktSize::6 14050 # Read request sizes (log2)
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system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::6 14046 # Write request sizes (log2)
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system.mem_ctrls.rdQLenPdf::0 3689 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::15 25 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::16 31 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::17 198 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::18 236 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::19 240 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::20 247 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::21 253 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::22 253 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::23 240 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::24 236 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::25 236 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::26 236 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::27 235 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::28 235 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::29 235 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::30 235 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::31 235 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::32 235 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.mem_ctrls.bytesPerActivate::samples 1249 # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::mean 383.846277 # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::gmean 248.755949 # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::stdev 339.416055 # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::0-127 261 20.90% 20.90% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::128-255 321 25.70% 46.60% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::256-383 184 14.73% 61.33% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::384-511 116 9.29% 70.62% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::512-639 64 5.12% 75.74% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::640-767 46 3.68% 79.42% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::768-895 41 3.28% 82.71% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::896-1023 34 2.72% 85.43% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::1024-1151 182 14.57% 100.00% # Bytes accessed per row activation
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system.mem_ctrls.bytesPerActivate::total 1249 # Bytes accessed per row activation
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system.mem_ctrls.rdPerTurnAround::samples 235 # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::mean 15.651064 # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::gmean 15.555359 # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::stdev 1.947371 # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::12-13 16 6.81% 6.81% # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::14-15 98 41.70% 48.51% # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::16-17 97 41.28% 89.79% # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::18-19 21 8.94% 98.72% # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::20-21 2 0.85% 99.57% # Reads before turning the bus around for writes
|
||
|
|
system.mem_ctrls.rdPerTurnAround::36-37 1 0.43% 100.00% # Reads before turning the bus around for writes
|
||
|
|
system.mem_ctrls.rdPerTurnAround::total 235 # Reads before turning the bus around for writes
|
||
|
|
system.mem_ctrls.wrPerTurnAround::samples 235 # Writes before turning the bus around for reads
|
||
|
|
system.mem_ctrls.wrPerTurnAround::mean 16.293617 # Writes before turning the bus around for reads
|
||
|
|
system.mem_ctrls.wrPerTurnAround::gmean 16.273674 # Writes before turning the bus around for reads
|
||
|
|
system.mem_ctrls.wrPerTurnAround::stdev 0.844136 # Writes before turning the bus around for reads
|
||
|
|
system.mem_ctrls.wrPerTurnAround::16 208 88.51% 88.51% # Writes before turning the bus around for reads
|
||
|
|
system.mem_ctrls.wrPerTurnAround::18 14 5.96% 94.47% # Writes before turning the bus around for reads
|
||
|
|
system.mem_ctrls.wrPerTurnAround::19 11 4.68% 99.15% # Writes before turning the bus around for reads
|
||
|
|
system.mem_ctrls.wrPerTurnAround::20 2 0.85% 100.00% # Writes before turning the bus around for reads
|
||
|
|
system.mem_ctrls.wrPerTurnAround::total 235 # Writes before turning the bus around for reads
|
||
|
|
system.mem_ctrls.totQLat 72649 # Total ticks spent queuing
|
||
|
|
system.mem_ctrls.totMemAccLat 142740 # Total ticks spent from burst creation until serviced by the DRAM
|
||
|
|
system.mem_ctrls.totBusLat 18445 # Total ticks spent in databus transfers
|
||
|
|
system.mem_ctrls.avgQLat 19.69 # Average queueing delay per DRAM burst
|
||
|
|
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||
|
|
system.mem_ctrls.avgMemAccLat 38.69 # Average memory access latency per DRAM burst
|
||
|
|
system.mem_ctrls.avgRdBW 296.59 # Average DRAM read bandwidth in MiByte/s
|
||
|
|
system.mem_ctrls.avgWrBW 307.85 # Average achieved write bandwidth in MiByte/s
|
||
|
|
system.mem_ctrls.avgRdBWSys 1129.60 # Average system read bandwidth in MiByte/s
|
||
|
|
system.mem_ctrls.avgWrBWSys 1129.28 # Average system write bandwidth in MiByte/s
|
||
|
|
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||
|
|
system.mem_ctrls.busUtil 4.72 # Data bus utilization in percentage
|
||
|
|
system.mem_ctrls.busUtilRead 2.32 # Data bus utilization in percentage for reads
|
||
|
|
system.mem_ctrls.busUtilWrite 2.41 # Data bus utilization in percentage for writes
|
||
|
|
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||
|
|
system.mem_ctrls.avgWrQLen 25.57 # Average write queue length when enqueuing
|
||
|
|
system.mem_ctrls.readRowHits 2727 # Number of row buffer hits during reads
|
||
|
|
system.mem_ctrls.writeRowHits 3536 # Number of row buffer hits during writes
|
||
|
|
system.mem_ctrls.readRowHitRate 73.92 # Row buffer hit rate for reads
|
||
|
|
system.mem_ctrls.writeRowHitRate 91.70 # Row buffer hit rate for writes
|
||
|
|
system.mem_ctrls.avgGap 28.33 # Average gap between requests
|
||
|
|
system.mem_ctrls.pageHitRate 83.01 # Row buffer hit rate, read and write combined
|
||
|
|
system.mem_ctrls_0.actEnergy 3048780 # Energy for activate commands per rank (pJ)
|
||
|
|
system.mem_ctrls_0.preEnergy 1642200 # Energy for precharge commands per rank (pJ)
|
||
|
|
system.mem_ctrls_0.readEnergy 11503968 # Energy for read commands per rank (pJ)
|
||
|
|
system.mem_ctrls_0.writeEnergy 8694432 # Energy for write commands per rank (pJ)
|
||
|
|
system.mem_ctrls_0.refreshEnergy 44868720.000000 # Energy for refresh commands per rank (pJ)
|
||
|
|
system.mem_ctrls_0.actBackEnergy 54752376 # Energy for active background per rank (pJ)
|
||
|
|
system.mem_ctrls_0.preBackEnergy 1331712 # Energy for precharge background per rank (pJ)
|
||
|
|
system.mem_ctrls_0.actPowerDownEnergy 160437216 # Energy for active power-down per rank (pJ)
|
||
|
|
system.mem_ctrls_0.prePowerDownEnergy 26780160 # Energy for precharge power-down per rank (pJ)
|
||
|
|
system.mem_ctrls_0.selfRefreshEnergy 62430000 # Energy for self refresh per rank (pJ)
|
||
|
|
system.mem_ctrls_0.totalEnergy 375489564 # Total energy per rank (pJ)
|
||
|
|
system.mem_ctrls_0.averagePower 471.699225 # Core power per rank (mW)
|
||
|
|
system.mem_ctrls_0.totalIdleTime 672460 # Total Idle time Per DRAM Rank
|
||
|
|
system.mem_ctrls_0.memoryStateTime::IDLE 1456 # Time in different power states
|
||
|
|
system.mem_ctrls_0.memoryStateTime::REF 19004 # Time in different power states
|
||
|
|
system.mem_ctrls_0.memoryStateTime::SREF 250921 # Time in different power states
|
||
|
|
system.mem_ctrls_0.memoryStateTime::PRE_PDN 69740 # Time in different power states
|
||
|
|
system.mem_ctrls_0.memoryStateTime::ACT 103079 # Time in different power states
|
||
|
|
system.mem_ctrls_0.memoryStateTime::ACT_PDN 351836 # Time in different power states
|
||
|
|
system.mem_ctrls_1.actEnergy 5911920 # Energy for activate commands per rank (pJ)
|
||
|
|
system.mem_ctrls_1.preEnergy 3183936 # Energy for precharge commands per rank (pJ)
|
||
|
|
system.mem_ctrls_1.readEnergy 30639168 # Energy for read commands per rank (pJ)
|
||
|
|
system.mem_ctrls_1.writeEnergy 23285376 # Energy for write commands per rank (pJ)
|
||
|
|
system.mem_ctrls_1.refreshEnergy 61464000.000000 # Energy for refresh commands per rank (pJ)
|
||
|
|
system.mem_ctrls_1.actBackEnergy 65872392 # Energy for active background per rank (pJ)
|
||
|
|
system.mem_ctrls_1.preBackEnergy 2049024 # Energy for precharge background per rank (pJ)
|
||
|
|
system.mem_ctrls_1.actPowerDownEnergy 210691152 # Energy for active power-down per rank (pJ)
|
||
|
|
system.mem_ctrls_1.prePowerDownEnergy 47203968 # Energy for precharge power-down per rank (pJ)
|
||
|
|
system.mem_ctrls_1.selfRefreshEnergy 18571440 # Energy for self refresh per rank (pJ)
|
||
|
|
system.mem_ctrls_1.totalEnergy 468872376 # Total energy per rank (pJ)
|
||
|
|
system.mem_ctrls_1.averagePower 589.009010 # Core power per rank (mW)
|
||
|
|
system.mem_ctrls_1.totalIdleTime 646243 # Total Idle time Per DRAM Rank
|
||
|
|
system.mem_ctrls_1.memoryStateTime::IDLE 2396 # Time in different power states
|
||
|
|
system.mem_ctrls_1.memoryStateTime::REF 26042 # Time in different power states
|
||
|
|
system.mem_ctrls_1.memoryStateTime::SREF 61274 # Time in different power states
|
||
|
|
system.mem_ctrls_1.memoryStateTime::PRE_PDN 122927 # Time in different power states
|
||
|
|
system.mem_ctrls_1.memoryStateTime::ACT 121355 # Time in different power states
|
||
|
|
system.mem_ctrls_1.memoryStateTime::ACT_PDN 462042 # Time in different power states
|
||
|
|
system.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||
|
|
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
||
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
||
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
||
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
||
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||
|
|
system.cpu.dtb.hits 0 # DTB hits
|
||
|
|
system.cpu.dtb.misses 0 # DTB misses
|
||
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
||
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||
|
|
system.cpu.itb.hits 0 # DTB hits
|
||
|
|
system.cpu.itb.misses 0 # DTB misses
|
||
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
||
|
|
system.cpu.workload.num_syscalls 9 # Number of system calls
|
||
|
|
system.cpu.pwrStateResidencyTicks::ON 796036 # Cumulative time (in ticks) in various power states
|
||
|
|
system.cpu.numCycles 796036 # number of cpu cycles simulated
|
||
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||
|
|
system.cpu.committedInsts 66173 # Number of instructions committed
|
||
|
|
system.cpu.committedOps 66173 # Number of ops (including micro ops) committed
|
||
|
|
system.cpu.num_int_alu_accesses 66174 # Number of integer alu accesses
|
||
|
|
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||
|
|
system.cpu.num_func_calls 5169 # number of times a function call or return occured
|
||
|
|
system.cpu.num_conditional_control_insts 10311 # number of instructions that are conditional controls
|
||
|
|
system.cpu.num_int_insts 66174 # number of integer instructions
|
||
|
|
system.cpu.num_fp_insts 0 # number of float instructions
|
||
|
|
system.cpu.num_int_register_reads 89437 # number of times the integer registers were read
|
||
|
|
system.cpu.num_int_register_writes 43419 # number of times the integer registers were written
|
||
|
|
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||
|
|
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||
|
|
system.cpu.num_mem_refs 24255 # number of memory refs
|
||
|
|
system.cpu.num_load_insts 11810 # Number of load instructions
|
||
|
|
system.cpu.num_store_insts 12445 # Number of store instructions
|
||
|
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||
|
|
system.cpu.num_busy_cycles 796036 # Number of busy cycles
|
||
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||
|
|
system.cpu.Branches 15480 # Number of branches fetched
|
||
|
|
system.cpu.op_class::No_OpClass 9 0.01% 0.01% # Class of executed instruction
|
||
|
|
system.cpu.op_class::IntAlu 41896 63.30% 63.32% # Class of executed instruction
|
||
|
|
system.cpu.op_class::IntMult 15 0.02% 63.34% # Class of executed instruction
|
||
|
|
system.cpu.op_class::IntDiv 8 0.01% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatAdd 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatCmp 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatCvt 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatMult 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatMultAcc 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatDiv 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatMisc 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdAdd 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdAlu 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdCmp 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdCvt 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdMisc 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdMult 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdShift 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.35% # Class of executed instruction
|
||
|
|
system.cpu.op_class::MemRead 11810 17.84% 81.20% # Class of executed instruction
|
||
|
|
system.cpu.op_class::MemWrite 12445 18.80% 100.00% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
|
||
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||
|
|
system.cpu.op_class::total 66183 # Class of executed instruction
|
||
|
|
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||
|
|
system.ruby.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||
|
|
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
|
||
|
|
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
|
||
|
|
system.ruby.delayHist::samples 28096 # delay histogram for all message
|
||
|
|
system.ruby.delayHist | 28096 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||
|
|
system.ruby.delayHist::total 28096 # delay histogram for all message
|
||
|
|
system.ruby.outstanding_req_hist_seqr::bucket_size 1
|
||
|
|
system.ruby.outstanding_req_hist_seqr::max_bucket 9
|
||
|
|
system.ruby.outstanding_req_hist_seqr::samples 90437
|
||
|
|
system.ruby.outstanding_req_hist_seqr::mean 1
|
||
|
|
system.ruby.outstanding_req_hist_seqr::gmean 1
|
||
|
|
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 90437 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||
|
|
system.ruby.outstanding_req_hist_seqr::total 90437
|
||
|
|
system.ruby.latency_hist_seqr::bucket_size 64
|
||
|
|
system.ruby.latency_hist_seqr::max_bucket 639
|
||
|
|
system.ruby.latency_hist_seqr::samples 90436
|
||
|
|
system.ruby.latency_hist_seqr::mean 7.802203
|
||
|
|
system.ruby.latency_hist_seqr::gmean 1.774694
|
||
|
|
system.ruby.latency_hist_seqr::stdev 20.056111
|
||
|
|
system.ruby.latency_hist_seqr | 86872 96.06% 96.06% | 3313 3.66% 99.72% | 168 0.19% 99.91% | 27 0.03% 99.94% | 26 0.03% 99.97% | 19 0.02% 99.99% | 1 0.00% 99.99% | 1 0.00% 99.99% | 0 0.00% 99.99% | 9 0.01% 100.00%
|
||
|
|
system.ruby.latency_hist_seqr::total 90436
|
||
|
|
system.ruby.hit_latency_hist_seqr::bucket_size 1
|
||
|
|
system.ruby.hit_latency_hist_seqr::max_bucket 9
|
||
|
|
system.ruby.hit_latency_hist_seqr::samples 76386
|
||
|
|
system.ruby.hit_latency_hist_seqr::mean 1
|
||
|
|
system.ruby.hit_latency_hist_seqr::gmean 1
|
||
|
|
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 76386 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||
|
|
system.ruby.hit_latency_hist_seqr::total 76386
|
||
|
|
system.ruby.miss_latency_hist_seqr::bucket_size 64
|
||
|
|
system.ruby.miss_latency_hist_seqr::max_bucket 639
|
||
|
|
system.ruby.miss_latency_hist_seqr::samples 14050
|
||
|
|
system.ruby.miss_latency_hist_seqr::mean 44.783915
|
||
|
|
system.ruby.miss_latency_hist_seqr::gmean 40.136483
|
||
|
|
system.ruby.miss_latency_hist_seqr::stdev 31.144722
|
||
|
|
system.ruby.miss_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00%
|
||
|
|
system.ruby.miss_latency_hist_seqr::total 14050
|
||
|
|
system.ruby.Directory.incomplete_times_seqr 14049
|
||
|
|
system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||
|
|
system.ruby.l1_cntrl0.cacheMemory.demand_hits 76386 # Number of cache demand hits
|
||
|
|
system.ruby.l1_cntrl0.cacheMemory.demand_misses 14050 # Number of cache demand misses
|
||
|
|
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 90436 # Number of cache demand accesses
|
||
|
|
system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||
|
|
system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||
|
|
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||
|
|
system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||
|
|
system.ruby.network.routers0.percent_links_utilized 8.823722
|
||
|
|
system.ruby.network.routers0.msg_count.Control::2 14050
|
||
|
|
system.ruby.network.routers0.msg_count.Data::2 14046
|
||
|
|
system.ruby.network.routers0.msg_count.Response_Data::4 14050
|
||
|
|
system.ruby.network.routers0.msg_count.Writeback_Control::3 14046
|
||
|
|
system.ruby.network.routers0.msg_bytes.Control::2 112400
|
||
|
|
system.ruby.network.routers0.msg_bytes.Data::2 1011312
|
||
|
|
system.ruby.network.routers0.msg_bytes.Response_Data::4 1011600
|
||
|
|
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 112368
|
||
|
|
system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||
|
|
system.ruby.network.routers1.percent_links_utilized 8.823722
|
||
|
|
system.ruby.network.routers1.msg_count.Control::2 14050
|
||
|
|
system.ruby.network.routers1.msg_count.Data::2 14046
|
||
|
|
system.ruby.network.routers1.msg_count.Response_Data::4 14050
|
||
|
|
system.ruby.network.routers1.msg_count.Writeback_Control::3 14046
|
||
|
|
system.ruby.network.routers1.msg_bytes.Control::2 112400
|
||
|
|
system.ruby.network.routers1.msg_bytes.Data::2 1011312
|
||
|
|
system.ruby.network.routers1.msg_bytes.Response_Data::4 1011600
|
||
|
|
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 112368
|
||
|
|
system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||
|
|
system.ruby.network.routers2.percent_links_utilized 8.823722
|
||
|
|
system.ruby.network.routers2.msg_count.Control::2 14050
|
||
|
|
system.ruby.network.routers2.msg_count.Data::2 14046
|
||
|
|
system.ruby.network.routers2.msg_count.Response_Data::4 14050
|
||
|
|
system.ruby.network.routers2.msg_count.Writeback_Control::3 14046
|
||
|
|
system.ruby.network.routers2.msg_bytes.Control::2 112400
|
||
|
|
system.ruby.network.routers2.msg_bytes.Data::2 1011312
|
||
|
|
system.ruby.network.routers2.msg_bytes.Response_Data::4 1011600
|
||
|
|
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 112368
|
||
|
|
system.ruby.network.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||
|
|
system.ruby.network.msg_count.Control 42150
|
||
|
|
system.ruby.network.msg_count.Data 42138
|
||
|
|
system.ruby.network.msg_count.Response_Data 42150
|
||
|
|
system.ruby.network.msg_count.Writeback_Control 42138
|
||
|
|
system.ruby.network.msg_byte.Control 337200
|
||
|
|
system.ruby.network.msg_byte.Data 3033936
|
||
|
|
system.ruby.network.msg_byte.Response_Data 3034800
|
||
|
|
system.ruby.network.msg_byte.Writeback_Control 337104
|
||
|
|
system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
|
||
|
|
system.ruby.network.routers0.throttle0.link_utilization 8.824727
|
||
|
|
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 14050
|
||
|
|
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 14046
|
||
|
|
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 1011600
|
||
|
|
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 112368
|
||
|
|
system.ruby.network.routers0.throttle1.link_utilization 8.822717
|
||
|
|
system.ruby.network.routers0.throttle1.msg_count.Control::2 14050
|
||
|
|
system.ruby.network.routers0.throttle1.msg_count.Data::2 14046
|
||
|
|
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 112400
|
||
|
|
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 1011312
|
||
|
|
system.ruby.network.routers1.throttle0.link_utilization 8.822717
|
||
|
|
system.ruby.network.routers1.throttle0.msg_count.Control::2 14050
|
||
|
|
system.ruby.network.routers1.throttle0.msg_count.Data::2 14046
|
||
|
|
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 112400
|
||
|
|
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 1011312
|
||
|
|
system.ruby.network.routers1.throttle1.link_utilization 8.824727
|
||
|
|
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 14050
|
||
|
|
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 14046
|
||
|
|
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 1011600
|
||
|
|
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 112368
|
||
|
|
system.ruby.network.routers2.throttle0.link_utilization 8.824727
|
||
|
|
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 14050
|
||
|
|
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 14046
|
||
|
|
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 1011600
|
||
|
|
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 112368
|
||
|
|
system.ruby.network.routers2.throttle1.link_utilization 8.822717
|
||
|
|
system.ruby.network.routers2.throttle1.msg_count.Control::2 14050
|
||
|
|
system.ruby.network.routers2.throttle1.msg_count.Data::2 14046
|
||
|
|
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 112400
|
||
|
|
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 1011312
|
||
|
|
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
|
||
|
|
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
|
||
|
|
system.ruby.delayVCHist.vnet_1::samples 14050 # delay histogram for vnet_1
|
||
|
|
system.ruby.delayVCHist.vnet_1 | 14050 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||
|
|
system.ruby.delayVCHist.vnet_1::total 14050 # delay histogram for vnet_1
|
||
|
|
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
|
||
|
|
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
|
||
|
|
system.ruby.delayVCHist.vnet_2::samples 14046 # delay histogram for vnet_2
|
||
|
|
system.ruby.delayVCHist.vnet_2 | 14046 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||
|
|
system.ruby.delayVCHist.vnet_2::total 14046 # delay histogram for vnet_2
|
||
|
|
system.ruby.LD.latency_hist_seqr::bucket_size 64
|
||
|
|
system.ruby.LD.latency_hist_seqr::max_bucket 639
|
||
|
|
system.ruby.LD.latency_hist_seqr::samples 11809
|
||
|
|
system.ruby.LD.latency_hist_seqr::mean 15.856719
|
||
|
|
system.ruby.LD.latency_hist_seqr::gmean 3.539899
|
||
|
|
system.ruby.LD.latency_hist_seqr::stdev 26.045304
|
||
|
|
system.ruby.LD.latency_hist_seqr | 10771 91.21% 91.21% | 977 8.27% 99.48% | 43 0.36% 99.85% | 9 0.08% 99.92% | 5 0.04% 99.97% | 2 0.02% 99.98% | 0 0.00% 99.98% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00%
|
||
|
|
system.ruby.LD.latency_hist_seqr::total 11809
|
||
|
|
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
|
||
|
|
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
|
||
|
|
system.ruby.LD.hit_latency_hist_seqr::samples 7768
|
||
|
|
system.ruby.LD.hit_latency_hist_seqr::mean 1
|
||
|
|
system.ruby.LD.hit_latency_hist_seqr::gmean 1
|
||
|
|
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 7768 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||
|
|
system.ruby.LD.hit_latency_hist_seqr::total 7768
|
||
|
|
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
|
||
|
|
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
|
||
|
|
system.ruby.LD.miss_latency_hist_seqr::samples 4041
|
||
|
|
system.ruby.LD.miss_latency_hist_seqr::mean 44.415739
|
||
|
|
system.ruby.LD.miss_latency_hist_seqr::gmean 40.208159
|
||
|
|
system.ruby.LD.miss_latency_hist_seqr::stdev 27.248261
|
||
|
|
system.ruby.LD.miss_latency_hist_seqr | 3003 74.31% 74.31% | 977 24.18% 98.49% | 43 1.06% 99.55% | 9 0.22% 99.78% | 5 0.12% 99.90% | 2 0.05% 99.95% | 0 0.00% 99.95% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00%
|
||
|
|
system.ruby.LD.miss_latency_hist_seqr::total 4041
|
||
|
|
system.ruby.ST.latency_hist_seqr::bucket_size 64
|
||
|
|
system.ruby.ST.latency_hist_seqr::max_bucket 639
|
||
|
|
system.ruby.ST.latency_hist_seqr::samples 12443
|
||
|
|
system.ruby.ST.latency_hist_seqr::mean 11.799164
|
||
|
|
system.ruby.ST.latency_hist_seqr::gmean 2.546410
|
||
|
|
system.ruby.ST.latency_hist_seqr::stdev 25.562634
|
||
|
|
system.ruby.ST.latency_hist_seqr | 11787 94.73% 94.73% | 602 4.84% 99.57% | 31 0.25% 99.82% | 7 0.06% 99.87% | 4 0.03% 99.90% | 7 0.06% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 5 0.04% 100.00%
|
||
|
|
system.ruby.ST.latency_hist_seqr::total 12443
|
||
|
|
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
|
||
|
|
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
|
||
|
|
system.ruby.ST.hit_latency_hist_seqr::samples 9259
|
||
|
|
system.ruby.ST.hit_latency_hist_seqr::mean 1
|
||
|
|
system.ruby.ST.hit_latency_hist_seqr::gmean 1
|
||
|
|
system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 9259 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||
|
|
system.ruby.ST.hit_latency_hist_seqr::total 9259
|
||
|
|
system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
|
||
|
|
system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
|
||
|
|
system.ruby.ST.miss_latency_hist_seqr::samples 3184
|
||
|
|
system.ruby.ST.miss_latency_hist_seqr::mean 43.202889
|
||
|
|
system.ruby.ST.miss_latency_hist_seqr::gmean 38.579676
|
||
|
|
system.ruby.ST.miss_latency_hist_seqr::stdev 35.050159
|
||
|
|
system.ruby.ST.miss_latency_hist_seqr | 2528 79.40% 79.40% | 602 18.91% 98.30% | 31 0.97% 99.28% | 7 0.22% 99.50% | 4 0.13% 99.62% | 7 0.22% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.16% 100.00%
|
||
|
|
system.ruby.ST.miss_latency_hist_seqr::total 3184
|
||
|
|
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
|
||
|
|
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
|
||
|
|
system.ruby.IFETCH.latency_hist_seqr::samples 66183
|
||
|
|
system.ruby.IFETCH.latency_hist_seqr::mean 5.613677
|
||
|
|
system.ruby.IFETCH.latency_hist_seqr::gmean 1.466025
|
||
|
|
system.ruby.IFETCH.latency_hist_seqr::stdev 16.923600
|
||
|
|
system.ruby.IFETCH.latency_hist_seqr | 64313 97.17% 97.17% | 1734 2.62% 99.79% | 94 0.14% 99.94% | 11 0.02% 99.95% | 17 0.03% 99.98% | 10 0.02% 99.99% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00%
|
||
|
|
system.ruby.IFETCH.latency_hist_seqr::total 66183
|
||
|
|
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
|
||
|
|
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
|
||
|
|
system.ruby.IFETCH.hit_latency_hist_seqr::samples 59358
|
||
|
|
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
|
||
|
|
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
|
||
|
|
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 59358 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||
|
|
system.ruby.IFETCH.hit_latency_hist_seqr::total 59358
|
||
|
|
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
|
||
|
|
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
|
||
|
|
system.ruby.IFETCH.miss_latency_hist_seqr::samples 6825
|
||
|
|
system.ruby.IFETCH.miss_latency_hist_seqr::mean 45.739487
|
||
|
|
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 40.840935
|
||
|
|
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.340636
|
||
|
|
system.ruby.IFETCH.miss_latency_hist_seqr | 4955 72.60% 72.60% | 1734 25.41% 98.01% | 94 1.38% 99.38% | 11 0.16% 99.55% | 17 0.25% 99.79% | 10 0.15% 99.94% | 1 0.01% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 3 0.04% 100.00%
|
||
|
|
system.ruby.IFETCH.miss_latency_hist_seqr::total 6825
|
||
|
|
system.ruby.Load_Linked.latency_hist_seqr::bucket_size 1
|
||
|
|
system.ruby.Load_Linked.latency_hist_seqr::max_bucket 9
|
||
|
|
system.ruby.Load_Linked.latency_hist_seqr::samples 1
|
||
|
|
system.ruby.Load_Linked.latency_hist_seqr::mean 1
|
||
|
|
system.ruby.Load_Linked.latency_hist_seqr::gmean 1
|
||
|
|
system.ruby.Load_Linked.latency_hist_seqr::stdev nan
|
||
|
|
system.ruby.Load_Linked.latency_hist_seqr | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||
|
|
system.ruby.Load_Linked.latency_hist_seqr::total 1
|
||
|
|
system.ruby.Load_Linked.hit_latency_hist_seqr::bucket_size 1
|
||
|
|
system.ruby.Load_Linked.hit_latency_hist_seqr::max_bucket 9
|
||
|
|
system.ruby.Load_Linked.hit_latency_hist_seqr::samples 1
|
||
|
|
system.ruby.Load_Linked.hit_latency_hist_seqr::mean 1
|
||
|
|
system.ruby.Load_Linked.hit_latency_hist_seqr::gmean 1
|
||
|
|
system.ruby.Load_Linked.hit_latency_hist_seqr::stdev nan
|
||
|
|
system.ruby.Load_Linked.hit_latency_hist_seqr | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||
|
|
system.ruby.Load_Linked.hit_latency_hist_seqr::total 1
|
||
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
|
||
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
|
||
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 14050
|
||
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr::mean 44.783915
|
||
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 40.136483
|
||
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 31.144722
|
||
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00%
|
||
|
|
system.ruby.Directory.miss_mach_latency_hist_seqr::total 14050
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
||
|
|
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
|
||
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
|
||
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
|
||
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 4041
|
||
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 44.415739
|
||
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 40.208159
|
||
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.248261
|
||
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 3003 74.31% 74.31% | 977 24.18% 98.49% | 43 1.06% 99.55% | 9 0.22% 99.78% | 5 0.12% 99.90% | 2 0.05% 99.95% | 0 0.00% 99.95% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00%
|
||
|
|
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 4041
|
||
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
|
||
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
|
||
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 3184
|
||
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 43.202889
|
||
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 38.579676
|
||
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.050159
|
||
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 2528 79.40% 79.40% | 602 18.91% 98.30% | 31 0.97% 99.28% | 7 0.22% 99.50% | 4 0.13% 99.62% | 7 0.22% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.16% 100.00%
|
||
|
|
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 3184
|
||
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
|
||
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
|
||
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 6825
|
||
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 45.739487
|
||
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 40.840935
|
||
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 31.340636
|
||
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 4955 72.60% 72.60% | 1734 25.41% 98.01% | 94 1.38% 99.38% | 11 0.16% 99.55% | 17 0.25% 99.79% | 10 0.15% 99.94% | 1 0.01% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 3 0.04% 100.00%
|
||
|
|
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 6825
|
||
|
|
system.ruby.Directory_Controller.GETX 14050 0.00% 0.00%
|
||
|
|
system.ruby.Directory_Controller.PUTX 14046 0.00% 0.00%
|
||
|
|
system.ruby.Directory_Controller.Memory_Data 14050 0.00% 0.00%
|
||
|
|
system.ruby.Directory_Controller.Memory_Ack 14046 0.00% 0.00%
|
||
|
|
system.ruby.Directory_Controller.I.GETX 14050 0.00% 0.00%
|
||
|
|
system.ruby.Directory_Controller.M.PUTX 14046 0.00% 0.00%
|
||
|
|
system.ruby.Directory_Controller.IM.Memory_Data 14050 0.00% 0.00%
|
||
|
|
system.ruby.Directory_Controller.MI.Memory_Ack 14046 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.Load 11809 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.Ifetch 66183 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.Store 12444 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.Data 14050 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.Replacement 14046 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.Writeback_Ack 14046 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.I.Load 4041 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.I.Ifetch 6825 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.I.Store 3184 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.M.Load 7768 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.M.Ifetch 59358 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.M.Store 9260 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.M.Replacement 14046 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.MI.Writeback_Ack 14046 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.IS.Data 10866 0.00% 0.00%
|
||
|
|
system.ruby.L1Cache_Controller.IM.Data 3184 0.00% 0.00%
|
||
|
|
|
||
|
|
---------- End Simulation Statistics ----------
|