212 lines
3.9 KiB
INI
212 lines
3.9 KiB
INI
|
[root]
|
||
|
|
type=Root
|
||
|
|
children=system
|
||
|
|
eventq_index=0
|
||
|
|
full_system=false
|
||
|
|
sim_quantum=0
|
||
|
|
time_sync_enable=false
|
||
|
|
time_sync_period=100000000000
|
||
|
|
time_sync_spin_threshold=100000000
|
||
|
|
|
||
|
|
[system]
|
||
|
|
type=System
|
||
|
|
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
|
||
|
|
boot_osflags=a
|
||
|
|
cache_line_size=64
|
||
|
|
clk_domain=system.clk_domain
|
||
|
|
default_p_state=UNDEFINED
|
||
|
|
eventq_index=0
|
||
|
|
exit_on_work_items=false
|
||
|
|
init_param=0
|
||
|
|
kernel=
|
||
|
|
kernel_addr_check=true
|
||
|
|
load_addr_mask=1099511627775
|
||
|
|
load_offset=0
|
||
|
|
mem_mode=atomic
|
||
|
|
mem_ranges=
|
||
|
|
memories=system.physmem
|
||
|
|
mmap_using_noreserve=false
|
||
|
|
multi_thread=false
|
||
|
|
num_work_ids=16
|
||
|
|
p_state_clk_gate_bins=20
|
||
|
|
p_state_clk_gate_max=1000000000000
|
||
|
|
p_state_clk_gate_min=1000
|
||
|
|
power_model=Null
|
||
|
|
readfile=
|
||
|
|
symbolfile=
|
||
|
|
thermal_components=
|
||
|
|
thermal_model=Null
|
||
|
|
work_begin_ckpt_count=0
|
||
|
|
work_begin_cpu_id_exit=-1
|
||
|
|
work_begin_exit_count=0
|
||
|
|
work_cpus_ckpt_count=0
|
||
|
|
work_end_ckpt_count=0
|
||
|
|
work_end_exit_count=0
|
||
|
|
work_item_id=-1
|
||
|
|
system_port=system.membus.slave[0]
|
||
|
|
|
||
|
|
[system.clk_domain]
|
||
|
|
type=SrcClockDomain
|
||
|
|
clock=1000
|
||
|
|
domain_id=-1
|
||
|
|
eventq_index=0
|
||
|
|
init_perf_level=0
|
||
|
|
voltage_domain=system.voltage_domain
|
||
|
|
|
||
|
|
[system.cpu]
|
||
|
|
type=AtomicSimpleCPU
|
||
|
|
children=dtb interrupts isa itb tracer workload
|
||
|
|
branchPred=Null
|
||
|
|
checker=Null
|
||
|
|
clk_domain=system.cpu_clk_domain
|
||
|
|
cpu_id=0
|
||
|
|
default_p_state=UNDEFINED
|
||
|
|
do_checkpoint_insts=true
|
||
|
|
do_quiesce=true
|
||
|
|
do_statistics_insts=true
|
||
|
|
dtb=system.cpu.dtb
|
||
|
|
eventq_index=0
|
||
|
|
fastmem=false
|
||
|
|
function_trace=false
|
||
|
|
function_trace_start=0
|
||
|
|
interrupts=system.cpu.interrupts
|
||
|
|
isa=system.cpu.isa
|
||
|
|
itb=system.cpu.itb
|
||
|
|
max_insts_all_threads=0
|
||
|
|
max_insts_any_thread=0
|
||
|
|
max_loads_all_threads=0
|
||
|
|
max_loads_any_thread=0
|
||
|
|
numThreads=1
|
||
|
|
p_state_clk_gate_bins=20
|
||
|
|
p_state_clk_gate_max=1000000000000
|
||
|
|
p_state_clk_gate_min=1000
|
||
|
|
power_model=Null
|
||
|
|
profile=0
|
||
|
|
progress_interval=0
|
||
|
|
simpoint_start_insts=
|
||
|
|
simulate_data_stalls=false
|
||
|
|
simulate_inst_stalls=false
|
||
|
|
socket_id=0
|
||
|
|
switched_out=false
|
||
|
|
system=system
|
||
|
|
tracer=system.cpu.tracer
|
||
|
|
width=1
|
||
|
|
workload=system.cpu.workload
|
||
|
|
dcache_port=system.membus.slave[2]
|
||
|
|
icache_port=system.membus.slave[1]
|
||
|
|
|
||
|
|
[system.cpu.dtb]
|
||
|
|
type=RiscvTLB
|
||
|
|
eventq_index=0
|
||
|
|
size=64
|
||
|
|
|
||
|
|
[system.cpu.interrupts]
|
||
|
|
type=RiscvInterrupts
|
||
|
|
eventq_index=0
|
||
|
|
|
||
|
|
[system.cpu.isa]
|
||
|
|
type=RiscvISA
|
||
|
|
eventq_index=0
|
||
|
|
|
||
|
|
[system.cpu.itb]
|
||
|
|
type=RiscvTLB
|
||
|
|
eventq_index=0
|
||
|
|
size=64
|
||
|
|
|
||
|
|
[system.cpu.tracer]
|
||
|
|
type=ExeTracer
|
||
|
|
eventq_index=0
|
||
|
|
|
||
|
|
[system.cpu.workload]
|
||
|
|
type=LiveProcess
|
||
|
|
cmd=insttest
|
||
|
|
cwd=
|
||
|
|
drivers=
|
||
|
|
egid=100
|
||
|
|
env=
|
||
|
|
errout=cerr
|
||
|
|
euid=100
|
||
|
|
eventq_index=0
|
||
|
|
executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest
|
||
|
|
gid=100
|
||
|
|
input=cin
|
||
|
|
kvmInSE=false
|
||
|
|
max_stack_size=67108864
|
||
|
|
output=cout
|
||
|
|
pid=100
|
||
|
|
ppid=99
|
||
|
|
simpoint=0
|
||
|
|
system=system
|
||
|
|
uid=100
|
||
|
|
useArchPT=false
|
||
|
|
|
||
|
|
[system.cpu_clk_domain]
|
||
|
|
type=SrcClockDomain
|
||
|
|
clock=500
|
||
|
|
domain_id=-1
|
||
|
|
eventq_index=0
|
||
|
|
init_perf_level=0
|
||
|
|
voltage_domain=system.voltage_domain
|
||
|
|
|
||
|
|
[system.dvfs_handler]
|
||
|
|
type=DVFSHandler
|
||
|
|
domains=
|
||
|
|
enable=false
|
||
|
|
eventq_index=0
|
||
|
|
sys_clk_domain=system.clk_domain
|
||
|
|
transition_latency=100000000
|
||
|
|
|
||
|
|
[system.membus]
|
||
|
|
type=CoherentXBar
|
||
|
|
children=snoop_filter
|
||
|
|
clk_domain=system.clk_domain
|
||
|
|
default_p_state=UNDEFINED
|
||
|
|
eventq_index=0
|
||
|
|
forward_latency=4
|
||
|
|
frontend_latency=3
|
||
|
|
p_state_clk_gate_bins=20
|
||
|
|
p_state_clk_gate_max=1000000000000
|
||
|
|
p_state_clk_gate_min=1000
|
||
|
|
point_of_coherency=true
|
||
|
|
power_model=Null
|
||
|
|
response_latency=2
|
||
|
|
snoop_filter=system.membus.snoop_filter
|
||
|
|
snoop_response_latency=4
|
||
|
|
system=system
|
||
|
|
use_default_range=false
|
||
|
|
width=16
|
||
|
|
master=system.physmem.port
|
||
|
|
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||
|
|
|
||
|
|
[system.membus.snoop_filter]
|
||
|
|
type=SnoopFilter
|
||
|
|
eventq_index=0
|
||
|
|
lookup_latency=1
|
||
|
|
max_capacity=8388608
|
||
|
|
system=system
|
||
|
|
|
||
|
|
[system.physmem]
|
||
|
|
type=SimpleMemory
|
||
|
|
bandwidth=73.000000
|
||
|
|
clk_domain=system.clk_domain
|
||
|
|
conf_table_reported=true
|
||
|
|
default_p_state=UNDEFINED
|
||
|
|
eventq_index=0
|
||
|
|
in_addr_map=true
|
||
|
|
kvm_map=true
|
||
|
|
latency=30000
|
||
|
|
latency_var=0
|
||
|
|
null=false
|
||
|
|
p_state_clk_gate_bins=20
|
||
|
|
p_state_clk_gate_max=1000000000000
|
||
|
|
p_state_clk_gate_min=1000
|
||
|
|
power_model=Null
|
||
|
|
range=0:134217727:0:0:0:0
|
||
|
|
port=system.membus.master[0]
|
||
|
|
|
||
|
|
[system.voltage_domain]
|
||
|
|
type=VoltageDomain
|
||
|
|
eventq_index=0
|
||
|
|
voltage=1.000000
|
||
|
|
|