104 lines
4.1 KiB
C++
104 lines
4.1 KiB
C++
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/*
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* Copyright (c) 2011-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2015 The University of Bologna
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erfan Azarkhish
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*/
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/**
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* @file
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* HMCController declaration
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*/
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#ifndef __HMC_CONTROLLER__
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#define __HMC_CONTROLLER__
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#include "mem/noncoherent_xbar.hh"
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#include "mem/port.hh"
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#include "params/HMCController.hh"
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/**
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* HMC Controller, in general, is responsible for translating the host
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* protocol (AXI for example) to serial links protocol. Plus, it should have
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* large internal buffers to hide the access latency of the cube. It is also
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* inferred from the standard [1] and the literature [2] that serial links
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* share the same address range and packets can travel over any of them, so a
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* load distribution mechanism is required.
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* This model simply queues the incoming transactions (using a Bridge) and
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* schedules them to the serial links using a simple round robin mechanism to
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* balance the load among them. More advanced global scheduling policies and
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* reordering and steering of transactions can be added to this model if
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* required [3].
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* [1] http://www.hybridmemorycube.org/specification-download/
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* [2] Low-Power Hybrid Memory Cubes With Link Power Manageme and Two-Level
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* Prefetching (J. Ahn et. al)
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* [3] The Open-Silicon HMC Controller IP
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* http://www.open-silicon.com/open-silicon-ips/hmc/
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*/
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class HMCController : public NoncoherentXBar
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{
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public:
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HMCController(const HMCControllerParams *p);
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private:
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// Receive range change only on one of the ports (because they all have
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// the same range)
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virtual void recvRangeChange(PortID master_port_id);
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// Receive a request and distribute it among slave ports
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// Simply forwards the packet to the next serial link based on a
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// Round-robin counter
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virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
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int n_master_ports;
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// The round-robin counter
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int rr_counter;
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/**
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* Function for rotating the round robin counter
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* @return the next value of the counter
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*/
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int rotate_counter();
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};
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#endif //__HMC_CONTROLLER__
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