2013-08-19 09:52:25 +02:00
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# Copyright (c) 2012-2013 ARM Limited
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2012-04-06 19:46:31 +02:00
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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2008-04-10 20:44:52 +02:00
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# Copyright (c) 2005-2008 The Regents of The University of Michigan
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2007-05-28 04:21:17 +02:00
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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2012-04-06 19:46:31 +02:00
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# Andreas Hansson
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2007-05-28 04:21:17 +02:00
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from m5.params import *
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2012-04-06 19:46:31 +02:00
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from AbstractMemory import *
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2007-05-28 04:21:17 +02:00
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2012-04-06 19:46:31 +02:00
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class SimpleMemory(AbstractMemory):
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type = 'SimpleMemory'
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2012-11-02 17:32:01 +01:00
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cxx_header = "mem/simple_mem.hh"
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2012-07-12 18:56:13 +02:00
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port = SlavePort("Slave ports")
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2012-04-06 19:46:31 +02:00
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latency = Param.Latency('30ns', "Request to response latency")
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latency_var = Param.Latency('0ns', "Request to response latency variance")
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2012-09-18 16:30:02 +02:00
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# The memory bandwidth limit default is set to 12.8GB/s which is
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# representative of a x64 DDR3-1600 channel.
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bandwidth = Param.MemoryBandwidth('12.8GB/s',
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"Combined read and write bandwidth")
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