Decode: Pull instruction decoding out of the StaticInst class into its own.
This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.
Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.
Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
2011-09-09 11:30:01 +02:00
|
|
|
/*
|
2012-05-25 09:53:37 +02:00
|
|
|
* Copyright (c) 2012 Google
|
Decode: Pull instruction decoding out of the StaticInst class into its own.
This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.
Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.
Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
2011-09-09 11:30:01 +02:00
|
|
|
* All rights reserved.
|
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions are
|
|
|
|
* met: redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer;
|
|
|
|
* redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
* documentation and/or other materials provided with the distribution;
|
|
|
|
* neither the name of the copyright holders nor the names of its
|
|
|
|
* contributors may be used to endorse or promote products derived from
|
|
|
|
* this software without specific prior written permission.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
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|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
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|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
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*
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|
|
* Authors: Gabe Black
|
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|
|
*/
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|
|
|
2012-05-25 09:53:37 +02:00
|
|
|
#ifndef __ARCH_X86_DECODER_HH__
|
|
|
|
#define __ARCH_X86_DECODER_HH__
|
Decode: Pull instruction decoding out of the StaticInst class into its own.
This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.
Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.
Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
2011-09-09 11:30:01 +02:00
|
|
|
|
2012-05-26 22:44:46 +02:00
|
|
|
#include <cassert>
|
2013-01-05 02:00:44 +01:00
|
|
|
#include <vector>
|
2012-05-26 22:44:46 +02:00
|
|
|
|
|
|
|
#include "arch/x86/regs/misc.hh"
|
|
|
|
#include "arch/x86/types.hh"
|
|
|
|
#include "base/bitfield.hh"
|
|
|
|
#include "base/misc.hh"
|
|
|
|
#include "base/trace.hh"
|
|
|
|
#include "base/types.hh"
|
2012-05-25 09:55:24 +02:00
|
|
|
#include "cpu/decode_cache.hh"
|
2012-05-26 22:45:12 +02:00
|
|
|
#include "cpu/static_inst.hh"
|
2012-05-26 22:44:46 +02:00
|
|
|
#include "debug/Decoder.hh"
|
|
|
|
|
2012-05-25 09:53:37 +02:00
|
|
|
namespace X86ISA
|
|
|
|
{
|
|
|
|
|
2012-05-25 09:55:24 +02:00
|
|
|
class Decoder
|
|
|
|
{
|
2012-05-26 22:44:46 +02:00
|
|
|
private:
|
|
|
|
//These are defined and documented in decoder_tables.cc
|
|
|
|
static const uint8_t Prefixes[256];
|
|
|
|
static const uint8_t UsesModRM[2][256];
|
|
|
|
static const uint8_t ImmediateType[2][256];
|
|
|
|
static const uint8_t SizeTypeToSize[3][10];
|
|
|
|
|
|
|
|
protected:
|
2013-01-05 02:00:44 +01:00
|
|
|
struct InstBytes
|
|
|
|
{
|
|
|
|
StaticInstPtr si;
|
|
|
|
std::vector<MachInst> chunks;
|
|
|
|
std::vector<MachInst> masks;
|
|
|
|
int lastOffset;
|
|
|
|
|
|
|
|
InstBytes() : lastOffset(0)
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
|
|
|
static InstBytes dummy;
|
|
|
|
|
2012-05-26 22:44:46 +02:00
|
|
|
//The bytes to be predecoded
|
|
|
|
MachInst fetchChunk;
|
2013-01-05 02:00:44 +01:00
|
|
|
InstBytes *instBytes;
|
|
|
|
int chunkIdx;
|
2012-05-26 22:44:46 +02:00
|
|
|
//The pc of the start of fetchChunk
|
|
|
|
Addr basePC;
|
|
|
|
//The pc the current instruction started at
|
|
|
|
Addr origPC;
|
|
|
|
//The offset into fetchChunk of current processing
|
|
|
|
int offset;
|
|
|
|
//The extended machine instruction being generated
|
|
|
|
ExtMachInst emi;
|
2013-01-05 02:00:44 +01:00
|
|
|
//Predecoding state
|
|
|
|
X86Mode mode;
|
|
|
|
X86SubMode submode;
|
|
|
|
uint8_t altOp;
|
|
|
|
uint8_t defOp;
|
|
|
|
uint8_t altAddr;
|
|
|
|
uint8_t defAddr;
|
|
|
|
uint8_t stack;
|
|
|
|
|
|
|
|
uint8_t getNextByte()
|
2012-05-26 22:44:46 +02:00
|
|
|
{
|
|
|
|
return ((uint8_t *)&fetchChunk)[offset];
|
|
|
|
}
|
|
|
|
|
|
|
|
void getImmediate(int &collected, uint64_t ¤t, int size)
|
|
|
|
{
|
|
|
|
//Figure out how many bytes we still need to get for the
|
|
|
|
//immediate.
|
|
|
|
int toGet = size - collected;
|
|
|
|
//Figure out how many bytes are left in our "buffer"
|
|
|
|
int remaining = sizeof(MachInst) - offset;
|
|
|
|
//Get as much as we need, up to the amount available.
|
|
|
|
toGet = toGet > remaining ? remaining : toGet;
|
|
|
|
|
|
|
|
//Shift the bytes we want to be all the way to the right
|
|
|
|
uint64_t partialImm = fetchChunk >> (offset * 8);
|
|
|
|
//Mask off what we don't want
|
|
|
|
partialImm &= mask(toGet * 8);
|
|
|
|
//Shift it over to overlay with our displacement.
|
|
|
|
partialImm <<= (immediateCollected * 8);
|
|
|
|
//Put it into our displacement
|
|
|
|
current |= partialImm;
|
|
|
|
//Update how many bytes we've collected.
|
|
|
|
collected += toGet;
|
|
|
|
consumeBytes(toGet);
|
|
|
|
}
|
|
|
|
|
2013-01-05 02:00:44 +01:00
|
|
|
void updateOffsetState()
|
2012-05-26 22:44:46 +02:00
|
|
|
{
|
|
|
|
assert(offset <= sizeof(MachInst));
|
2013-01-05 02:00:44 +01:00
|
|
|
if (offset == sizeof(MachInst)) {
|
|
|
|
DPRINTF(Decoder, "At the end of a chunk, idx = %d, chunks = %d.\n",
|
|
|
|
chunkIdx, instBytes->chunks.size());
|
|
|
|
chunkIdx++;
|
|
|
|
if (chunkIdx == instBytes->chunks.size()) {
|
|
|
|
outOfBytes = true;
|
|
|
|
} else {
|
|
|
|
offset = 0;
|
|
|
|
fetchChunk = instBytes->chunks[chunkIdx];
|
|
|
|
basePC += sizeof(MachInst);
|
|
|
|
}
|
|
|
|
}
|
2012-05-26 22:44:46 +02:00
|
|
|
}
|
|
|
|
|
2013-01-05 02:00:44 +01:00
|
|
|
void consumeByte()
|
2012-05-26 22:44:46 +02:00
|
|
|
{
|
2013-01-05 02:00:44 +01:00
|
|
|
offset++;
|
|
|
|
updateOffsetState();
|
2012-05-26 22:44:46 +02:00
|
|
|
}
|
|
|
|
|
2013-01-05 02:00:44 +01:00
|
|
|
void consumeBytes(int numBytes)
|
|
|
|
{
|
|
|
|
offset += numBytes;
|
|
|
|
updateOffsetState();
|
|
|
|
}
|
2012-05-26 22:44:46 +02:00
|
|
|
|
|
|
|
//State machine state
|
|
|
|
protected:
|
|
|
|
//Whether or not we're out of bytes
|
|
|
|
bool outOfBytes;
|
|
|
|
//Whether we've completed generating an ExtMachInst
|
|
|
|
bool instDone;
|
|
|
|
//The size of the displacement value
|
|
|
|
int displacementSize;
|
|
|
|
//The size of the immediate value
|
|
|
|
int immediateSize;
|
|
|
|
//This is how much of any immediate value we've gotten. This is used
|
|
|
|
//for both the actual immediate and the displacement.
|
|
|
|
int immediateCollected;
|
|
|
|
|
|
|
|
enum State {
|
|
|
|
ResetState,
|
2013-01-05 02:00:44 +01:00
|
|
|
FromCacheState,
|
2012-05-26 22:44:46 +02:00
|
|
|
PrefixState,
|
|
|
|
OpcodeState,
|
|
|
|
ModRMState,
|
|
|
|
SIBState,
|
|
|
|
DisplacementState,
|
|
|
|
ImmediateState,
|
|
|
|
//We should never get to this state. Getting here is an error.
|
|
|
|
ErrorState
|
|
|
|
};
|
|
|
|
|
|
|
|
State state;
|
|
|
|
|
|
|
|
//Functions to handle each of the states
|
2013-01-05 02:00:44 +01:00
|
|
|
State doResetState();
|
|
|
|
State doFromCacheState();
|
2012-05-26 22:44:46 +02:00
|
|
|
State doPrefixState(uint8_t);
|
|
|
|
State doOpcodeState(uint8_t);
|
|
|
|
State doModRMState(uint8_t);
|
|
|
|
State doSIBState(uint8_t);
|
|
|
|
State doDisplacementState();
|
|
|
|
State doImmediateState();
|
|
|
|
|
2013-01-05 02:00:44 +01:00
|
|
|
protected:
|
|
|
|
/// Caching for decoded instruction objects.
|
|
|
|
|
|
|
|
typedef MiscReg CacheKey;
|
|
|
|
|
|
|
|
typedef DecodeCache::AddrMap<Decoder::InstBytes> DecodePages;
|
|
|
|
DecodePages *decodePages;
|
|
|
|
typedef m5::hash_map<CacheKey, DecodePages *> AddrCacheMap;
|
|
|
|
AddrCacheMap addrCacheMap;
|
|
|
|
|
|
|
|
DecodeCache::InstMap *instMap;
|
|
|
|
typedef m5::hash_map<CacheKey, DecodeCache::InstMap *> InstCacheMap;
|
|
|
|
static InstCacheMap instCacheMap;
|
|
|
|
|
2012-05-26 22:44:46 +02:00
|
|
|
public:
|
2013-01-05 02:00:45 +01:00
|
|
|
Decoder() : basePC(0), origPC(0), offset(0),
|
2012-05-26 22:44:46 +02:00
|
|
|
outOfBytes(true), instDone(false),
|
|
|
|
state(ResetState)
|
|
|
|
{
|
2012-06-04 19:43:08 +02:00
|
|
|
memset(&emi, 0, sizeof(emi));
|
2013-01-05 02:00:44 +01:00
|
|
|
mode = LongMode;
|
|
|
|
submode = SixtyFourBitMode;
|
|
|
|
emi.mode.mode = mode;
|
|
|
|
emi.mode.submode = submode;
|
|
|
|
altOp = 0;
|
|
|
|
defOp = 0;
|
|
|
|
altAddr = 0;
|
|
|
|
defAddr = 0;
|
|
|
|
stack = 0;
|
|
|
|
instBytes = &dummy;
|
|
|
|
decodePages = NULL;
|
|
|
|
instMap = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
void setM5Reg(HandyM5Reg m5Reg)
|
|
|
|
{
|
|
|
|
mode = (X86Mode)(uint64_t)m5Reg.mode;
|
|
|
|
submode = (X86SubMode)(uint64_t)m5Reg.submode;
|
|
|
|
emi.mode.mode = mode;
|
|
|
|
emi.mode.submode = submode;
|
|
|
|
altOp = m5Reg.altOp;
|
|
|
|
defOp = m5Reg.defOp;
|
|
|
|
altAddr = m5Reg.altAddr;
|
|
|
|
defAddr = m5Reg.defAddr;
|
|
|
|
stack = m5Reg.stack;
|
|
|
|
|
|
|
|
AddrCacheMap::iterator amIter = addrCacheMap.find(m5Reg);
|
|
|
|
if (amIter != addrCacheMap.end()) {
|
|
|
|
decodePages = amIter->second;
|
|
|
|
} else {
|
|
|
|
decodePages = new DecodePages;
|
|
|
|
addrCacheMap[m5Reg] = decodePages;
|
|
|
|
}
|
|
|
|
|
|
|
|
InstCacheMap::iterator imIter = instCacheMap.find(m5Reg);
|
|
|
|
if (imIter != instCacheMap.end()) {
|
|
|
|
instMap = imIter->second;
|
|
|
|
} else {
|
|
|
|
instMap = new DecodeCache::InstMap;
|
|
|
|
instCacheMap[m5Reg] = instMap;
|
|
|
|
}
|
2012-05-26 22:44:46 +02:00
|
|
|
}
|
|
|
|
|
2013-01-22 07:10:10 +01:00
|
|
|
void takeOverFrom(Decoder *old)
|
|
|
|
{
|
|
|
|
mode = old->mode;
|
|
|
|
submode = old->submode;
|
|
|
|
emi.mode.mode = mode;
|
|
|
|
emi.mode.submode = submode;
|
|
|
|
altOp = old->altOp;
|
|
|
|
defOp = old->defOp;
|
|
|
|
altAddr = old->altAddr;
|
|
|
|
defAddr = old->defAddr;
|
|
|
|
stack = old->stack;
|
|
|
|
}
|
|
|
|
|
2012-05-26 22:44:46 +02:00
|
|
|
void reset()
|
|
|
|
{
|
|
|
|
state = ResetState;
|
|
|
|
}
|
|
|
|
|
|
|
|
void process();
|
|
|
|
|
|
|
|
//Use this to give data to the decoder. This should be used
|
|
|
|
//when there is control flow.
|
|
|
|
void moreBytes(const PCState &pc, Addr fetchPC, MachInst data)
|
|
|
|
{
|
|
|
|
DPRINTF(Decoder, "Getting more bytes.\n");
|
|
|
|
basePC = fetchPC;
|
|
|
|
offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
|
|
|
|
fetchChunk = data;
|
|
|
|
outOfBytes = false;
|
|
|
|
process();
|
|
|
|
}
|
|
|
|
|
|
|
|
bool needMoreBytes()
|
|
|
|
{
|
|
|
|
return outOfBytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool instReady()
|
|
|
|
{
|
|
|
|
return instDone;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
updateNPC(X86ISA::PCState &nextPC)
|
|
|
|
{
|
|
|
|
if (!nextPC.size()) {
|
|
|
|
int size = basePC + offset - origPC;
|
|
|
|
DPRINTF(Decoder,
|
|
|
|
"Calculating the instruction size: "
|
|
|
|
"basePC: %#x offset: %#x origPC: %#x size: %d\n",
|
|
|
|
basePC, offset, origPC, size);
|
|
|
|
nextPC.size(size);
|
|
|
|
nextPC.npc(nextPC.pc() + size);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-05-25 09:55:24 +02:00
|
|
|
public:
|
|
|
|
StaticInstPtr decodeInst(ExtMachInst mach_inst);
|
|
|
|
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/// Decode a machine instruction.
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/// @param mach_inst The binary instruction to decode.
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/// @retval A pointer to the corresponding StaticInst object.
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2012-05-26 22:45:12 +02:00
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StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
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2013-01-05 02:00:44 +01:00
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StaticInstPtr decode(X86ISA::PCState &nextPC);
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2012-05-25 09:55:24 +02:00
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};
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2012-05-25 09:53:37 +02:00
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} // namespace X86ISA
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#endif // __ARCH_X86_DECODER_HH__
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