2009-05-11 19:38:43 +02:00
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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2010-04-01 01:56:45 +02:00
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* The topology here is configurable; it can be a hierachical (default
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* one) or a 2D torus or a 2D torus with half switches killed. I think
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* all input port has a one-input-one-output switch connected just to
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* control and bandwidth, since we don't control bandwidth on input
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* ports. Basically, the class has a vector of nodes and edges. First
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* 2*m_nodes elements in the node vector are input and output
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* ports. Edges are represented in two vectors of src and dest
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* nodes. All edges have latency.
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*/
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2009-05-11 19:38:43 +02:00
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2010-04-01 01:56:45 +02:00
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#ifndef __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
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#define __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
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2009-05-11 19:38:43 +02:00
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2010-03-11 03:33:11 +01:00
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#include <iostream>
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#include <string>
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2010-06-11 08:17:07 +02:00
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#include <vector>
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2010-03-11 03:33:11 +01:00
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2011-04-29 02:18:14 +02:00
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#include "mem/protocol/LinkDirection.hh"
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2011-11-04 04:46:45 +01:00
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#include "mem/ruby/common/TypeDefines.hh"
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2012-10-02 21:35:45 +02:00
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#include "mem/ruby/network/BasicRouter.hh"
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2010-04-01 01:56:45 +02:00
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#include "params/Topology.hh"
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#include "sim/sim_object.hh"
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2009-05-11 19:38:43 +02:00
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class NetDest;
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2011-04-29 02:18:14 +02:00
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class Network;
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2009-05-11 19:38:43 +02:00
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2010-06-11 08:17:07 +02:00
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typedef std::vector<std::vector<int> > Matrix;
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2009-05-11 19:38:43 +02:00
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2011-04-29 02:18:14 +02:00
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struct LinkEntry
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2010-04-01 01:56:45 +02:00
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{
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2011-04-29 02:18:14 +02:00
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BasicLink *link;
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LinkDirection direction;
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2010-01-30 05:29:17 +01:00
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};
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2011-04-29 02:18:14 +02:00
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typedef std::map<std::pair<int, int>, LinkEntry> LinkMap;
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2010-01-30 05:29:17 +01:00
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2010-04-01 01:56:45 +02:00
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class Topology : public SimObject
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{
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public:
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2010-01-30 05:29:17 +01:00
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typedef TopologyParams Params;
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Topology(const Params *p);
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virtual ~Topology() {}
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2010-01-30 05:29:17 +01:00
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const Params *params() const { return (const Params *)_params; }
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2009-05-11 19:38:43 +02:00
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2011-04-29 02:18:14 +02:00
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void init();
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2010-04-01 01:56:45 +02:00
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int numSwitches() const { return m_number_of_switches; }
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void createLinks(Network *net, bool isReconfiguration);
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void initNetworkPtr(Network* net_ptr);
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const std::string getName() { return m_name; }
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void print(std::ostream& out) const { out << "[Topology]"; }
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protected:
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void addLink(SwitchID src, SwitchID dest, BasicLink* link,
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LinkDirection dir);
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2010-04-01 01:56:45 +02:00
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void makeLink(Network *net, SwitchID src, SwitchID dest,
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const NetDest& routing_table_entry,
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bool isReconfiguration);
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2010-04-01 01:56:45 +02:00
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std::string getDesignStr();
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// Private copy constructor and assignment operator
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Topology(const Topology& obj);
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Topology& operator=(const Topology& obj);
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std::string m_name;
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NodeID m_nodes;
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int m_number_of_switches;
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2011-04-29 02:18:14 +02:00
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std::vector<BasicExtLink*> m_ext_link_vector;
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std::vector<BasicIntLink*> m_int_link_vector;
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Matrix m_component_latencies;
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Matrix m_component_inter_switches;
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2011-04-29 02:18:14 +02:00
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LinkMap m_link_map;
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std::vector<BasicRouter*> m_router_vector;
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2009-05-11 19:38:43 +02:00
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};
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2010-04-01 01:56:45 +02:00
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inline std::ostream&
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operator<<(std::ostream& out, const Topology& obj)
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2009-05-11 19:38:43 +02:00
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{
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2010-04-01 01:56:45 +02:00
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obj.print(out);
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out << std::flush;
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return out;
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2009-05-11 19:38:43 +02:00
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}
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2010-04-01 01:56:45 +02:00
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#endif // __MEM_RUBY_NETWORK_SIMPLE_TOPOLOGY_HH__
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