2010-01-30 05:29:17 +01:00
|
|
|
/*
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
* Copyright (c) 2012 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
|
2010-01-30 05:29:17 +01:00
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* Copyright (c) 2009 Advanced Micro Devices, Inc.
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2012-01-23 18:07:14 +01:00
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* Copyright (c) 2011 Mark D. Hill and David A. Wood
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2010-01-30 05:29:17 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2010-03-23 02:43:53 +01:00
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#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
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#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
|
2009-07-07 00:49:47 +02:00
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|
2010-03-23 02:43:53 +01:00
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|
#include <cassert>
|
2009-07-07 00:49:47 +02:00
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#include <string>
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|
2010-01-30 05:29:33 +01:00
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#include "mem/protocol/RequestStatus.hh"
|
2011-02-07 07:14:18 +01:00
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#include "mem/ruby/system/System.hh"
|
2011-04-15 19:44:06 +02:00
|
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|
#include "mem/mem_object.hh"
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#include "mem/physical.hh"
|
2010-03-23 02:43:53 +01:00
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#include "mem/tport.hh"
|
2010-01-30 05:29:17 +01:00
|
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#include "params/RubyPort.hh"
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class MessageBuffer;
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|
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class AbstractController;
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|
2010-03-23 02:43:53 +01:00
|
|
|
class RubyPort : public MemObject
|
|
|
|
|
{
|
|
|
|
|
public:
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
class M5Port : public QueuedSlavePort
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
2010-03-23 02:43:53 +01:00
|
|
|
private:
|
2012-03-22 11:36:27 +01:00
|
|
|
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
SlavePacketQueue queue;
|
2010-01-30 05:29:19 +01:00
|
|
|
RubyPort *ruby_port;
|
2011-07-01 02:49:26 +02:00
|
|
|
RubySystem* ruby_system;
|
2011-02-07 07:14:18 +01:00
|
|
|
bool _onRetryList;
|
2011-02-07 07:14:19 +01:00
|
|
|
bool access_phys_mem;
|
2010-01-30 05:29:19 +01:00
|
|
|
|
|
|
|
|
public:
|
2011-02-07 07:14:19 +01:00
|
|
|
M5Port(const std::string &_name, RubyPort *_port,
|
2011-07-01 02:49:26 +02:00
|
|
|
RubySystem*_system, bool _access_phys_mem);
|
2010-01-30 05:29:19 +01:00
|
|
|
void hitCallback(PacketPtr pkt);
|
2012-01-23 18:07:14 +01:00
|
|
|
void evictionCallback(const Address& address);
|
2011-02-07 07:14:18 +01:00
|
|
|
unsigned deviceBlockSize() const;
|
2011-02-07 07:14:18 +01:00
|
|
|
|
|
|
|
|
bool onRetryList()
|
|
|
|
|
{ return _onRetryList; }
|
|
|
|
|
|
|
|
|
|
void onRetryList(bool newVal)
|
|
|
|
|
{ _onRetryList = newVal; }
|
2010-01-30 05:29:19 +01:00
|
|
|
|
|
|
|
|
protected:
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
virtual bool recvTimingReq(PacketPtr pkt);
|
2010-01-30 05:29:19 +01:00
|
|
|
virtual Tick recvAtomic(PacketPtr pkt);
|
2011-07-01 02:49:26 +02:00
|
|
|
virtual void recvFunctional(PacketPtr pkt);
|
2012-07-09 18:35:34 +02:00
|
|
|
virtual AddrRangeList getAddrRanges() const;
|
2010-01-30 05:29:19 +01:00
|
|
|
|
|
|
|
|
private:
|
|
|
|
|
bool isPhysMemAddress(Addr addr);
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
friend class M5Port;
|
|
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
class PioPort : public QueuedMasterPort
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
2010-03-23 02:43:53 +01:00
|
|
|
private:
|
2012-03-22 11:36:27 +01:00
|
|
|
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
MasterPacketQueue queue;
|
2012-03-22 11:36:27 +01:00
|
|
|
|
2010-01-30 05:29:19 +01:00
|
|
|
RubyPort *ruby_port;
|
|
|
|
|
|
|
|
|
|
public:
|
2010-03-23 02:43:53 +01:00
|
|
|
PioPort(const std::string &_name, RubyPort *_port);
|
2010-01-30 05:29:19 +01:00
|
|
|
|
|
|
|
|
protected:
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
virtual bool recvTimingResp(PacketPtr pkt);
|
2010-01-30 05:29:19 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
friend class PioPort;
|
|
|
|
|
|
|
|
|
|
struct SenderState : public Packet::SenderState
|
|
|
|
|
{
|
|
|
|
|
M5Port* port;
|
|
|
|
|
Packet::SenderState *saved;
|
|
|
|
|
|
2010-03-23 02:43:53 +01:00
|
|
|
SenderState(M5Port* _port, Packet::SenderState *sender_state = NULL)
|
2010-01-30 05:29:19 +01:00
|
|
|
: port(_port), saved(sender_state)
|
|
|
|
|
{}
|
|
|
|
|
};
|
|
|
|
|
|
2010-01-30 05:29:17 +01:00
|
|
|
typedef RubyPortParams Params;
|
|
|
|
|
RubyPort(const Params *p);
|
2010-01-30 05:29:19 +01:00
|
|
|
virtual ~RubyPort() {}
|
|
|
|
|
|
|
|
|
|
void init();
|
2009-07-07 00:49:47 +02:00
|
|
|
|
2012-10-15 14:12:35 +02:00
|
|
|
BaseMasterPort &getMasterPort(const std::string &if_name,
|
|
|
|
|
PortID idx = InvalidPortID);
|
|
|
|
|
BaseSlavePort &getSlavePort(const std::string &if_name,
|
|
|
|
|
PortID idx = InvalidPortID);
|
2010-01-30 05:29:17 +01:00
|
|
|
|
2011-11-15 00:44:35 +01:00
|
|
|
virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
|
2012-01-11 20:48:48 +01:00
|
|
|
virtual int outstandingCount() const = 0;
|
|
|
|
|
virtual bool isDeadlockEventScheduled() const = 0;
|
|
|
|
|
virtual void descheduleDeadlockEvent() = 0;
|
2010-01-30 05:29:19 +01:00
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Called by the controller to give the sequencer a pointer.
|
|
|
|
|
// A pointer to the controller is needed for atomic support.
|
|
|
|
|
//
|
|
|
|
|
void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
|
2012-01-11 20:48:48 +01:00
|
|
|
int getId() { return m_version; }
|
2012-11-02 17:32:01 +01:00
|
|
|
unsigned int drain(DrainManager *dm);
|
2009-07-07 00:49:47 +02:00
|
|
|
|
2010-03-23 02:43:53 +01:00
|
|
|
protected:
|
2010-04-02 20:20:32 +02:00
|
|
|
const std::string m_name;
|
2010-03-23 02:43:53 +01:00
|
|
|
void ruby_hit_callback(PacketPtr pkt);
|
2012-01-11 20:48:48 +01:00
|
|
|
void testDrainComplete();
|
2012-01-23 18:07:14 +01:00
|
|
|
void ruby_eviction_callback(const Address& address);
|
2009-07-07 00:49:47 +02:00
|
|
|
|
2010-03-23 02:43:53 +01:00
|
|
|
int m_version;
|
|
|
|
|
AbstractController* m_controller;
|
|
|
|
|
MessageBuffer* m_mandatory_q_ptr;
|
2012-02-24 17:43:53 +01:00
|
|
|
PioPort pio_port;
|
2011-02-07 07:14:18 +01:00
|
|
|
bool m_usingRubyTester;
|
2010-01-30 05:29:17 +01:00
|
|
|
|
2010-03-23 02:43:53 +01:00
|
|
|
private:
|
2011-02-07 07:14:18 +01:00
|
|
|
void addToRetryList(M5Port * port)
|
|
|
|
|
{
|
|
|
|
|
if (!port->onRetryList()) {
|
|
|
|
|
port->onRetryList(true);
|
|
|
|
|
retryList.push_back(port);
|
|
|
|
|
waitingOnSequencer = true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2012-11-02 17:32:01 +01:00
|
|
|
unsigned int getChildDrainCount(DrainManager *dm);
|
2012-01-11 20:48:48 +01:00
|
|
|
|
2010-01-30 05:29:33 +01:00
|
|
|
uint16_t m_port_id;
|
|
|
|
|
uint64_t m_request_cnt;
|
2010-01-30 05:29:19 +01:00
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
/** Vector of M5 Ports attached to this Ruby port. */
|
2012-01-11 20:39:58 +01:00
|
|
|
typedef std::vector<M5Port*>::iterator CpuPortIter;
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
std::vector<M5Port*> slave_ports;
|
|
|
|
|
std::vector<PioPort*> master_ports;
|
2012-01-11 20:39:58 +01:00
|
|
|
|
2012-11-02 17:32:01 +01:00
|
|
|
DrainManager *drainManager;
|
2012-01-11 20:48:48 +01:00
|
|
|
|
2011-07-01 02:49:26 +02:00
|
|
|
RubySystem* ruby_system;
|
2012-03-30 15:42:36 +02:00
|
|
|
System* system;
|
2011-02-07 07:14:18 +01:00
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Based on similar code in the M5 bus. Stores pointers to those ports
|
|
|
|
|
// that should be called when the Sequencer becomes available after a stall.
|
|
|
|
|
//
|
|
|
|
|
std::list<M5Port*> retryList;
|
|
|
|
|
|
|
|
|
|
bool waitingOnSequencer;
|
2011-02-07 07:14:19 +01:00
|
|
|
bool access_phys_mem;
|
2009-07-07 00:49:47 +02:00
|
|
|
};
|
|
|
|
|
|
2010-03-23 02:43:53 +01:00
|
|
|
#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
|
