2009-07-09 08:02:20 +02:00
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/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/mips/isa.hh"
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2009-07-10 05:28:39 +02:00
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#include "arch/mips/mt_constants.hh"
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#include "arch/mips/mt.hh"
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#include "arch/mips/pra_constants.hh"
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#include "base/bitfield.hh"
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#include "cpu/base.hh"
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2009-07-09 08:02:20 +02:00
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#include "cpu/thread_context.hh"
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namespace MipsISA
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{
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2009-07-10 05:28:39 +02:00
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std::string
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ISA::miscRegNames[NumMiscRegs] =
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{
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"Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
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"Random", "VPEControl", "VPEConf0", "VPEConf1",
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"YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
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"EntryLo0", "TCStatus", "TCBind", "TCRestart",
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"TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
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"EntryLo1", "", "", "", "", "", "", "",
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"Context", "ContextConfig", "", "", "", "", "", "",
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"PageMask", "PageGrain", "", "", "", "", "", "",
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"Wired", "SRSConf0", "SRCConf1", "SRSConf2",
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"SRSConf3", "SRSConf4", "", "",
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"HWREna", "", "", "", "", "", "", "",
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"BadVAddr", "", "", "", "", "", "", "",
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"Count", "", "", "", "", "", "", "",
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"EntryHi", "", "", "", "", "", "", "",
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"Compare", "", "", "", "", "", "", "",
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"Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
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"Cause", "", "", "", "", "", "", "",
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"EPC", "", "", "", "", "", "", "",
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"PRId", "EBase", "", "", "", "", "", "",
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"Config", "Config1", "Config2", "Config3", "", "", "", "",
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"LLAddr", "", "", "", "", "", "", "",
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"WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3",
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"WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
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"WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3",
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"WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
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"XCContext64", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"Debug", "TraceControl1", "TraceControl2", "UserTraceData",
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"TraceBPC", "", "", "",
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"DEPC", "", "", "", "", "", "", "",
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"PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3",
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"PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
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"ErrCtl", "", "", "", "", "", "", "",
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"CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
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"TagLo0", "DataLo1", "TagLo2", "DataLo3",
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"TagLo4", "DataLo5", "TagLo6", "DataLo7",
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"TagHi0", "DataHi1", "TagHi2", "DataHi3",
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"TagHi4", "DataHi5", "TagHi6", "DataHi7",
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"ErrorEPC", "", "", "", "", "", "", "",
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"DESAVE", "", "", "", "", "", "", "",
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"LLFlag"
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};
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ISA::ISA()
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{
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init();
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}
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ISA::ISA(BaseCPU *_cpu)
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{
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cpu = _cpu;
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init();
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}
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void
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ISA::init()
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{
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miscRegFile.resize(NumMiscRegs);
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bankType.resize(NumMiscRegs);
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for (int i=0; i < NumMiscRegs; i++) {
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miscRegFile[i].resize(1);
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bankType[i] = perProcessor;
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}
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miscRegFile_WriteMask.resize(NumMiscRegs);
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for (int i=0; i < NumMiscRegs; i++) {
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miscRegFile_WriteMask[i].push_back(0);
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}
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clear(0);
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}
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void
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ISA::clear(unsigned tid_or_vpn)
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{
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for(int i = 0; i < NumMiscRegs; i++) {
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miscRegFile[i][tid_or_vpn] = 0;
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miscRegFile_WriteMask[i][tid_or_vpn] = (long unsigned int)(-1);
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}
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}
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void
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ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
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{
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// Initialize all Per-VPE regs
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uint32_t per_vpe_regs[] = { VPEControl, VPEConf0, VPEConf1, YQMask,
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VPESchedule, VPEScheFBack, VPEOpt, SRSConf0,
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SRSConf1, SRSConf2, SRSConf3, SRSConf4,
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EBase
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};
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uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
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for (int i = 0; i < num_vpe_regs; i++) {
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if (num_vpes > 1) {
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miscRegFile[per_vpe_regs[i]].resize(num_vpes);
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}
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bankType[per_vpe_regs[i]] = perVirtProcessor;
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}
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// Initialize all Per-TC regs
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uint32_t per_tc_regs[] = { Status, TCStatus, TCBind, TCRestart, TCHalt,
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TCContext, TCSchedule, TCScheFBack, Debug,
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LLAddr
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};
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uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
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for (int i = 0; i < num_tc_regs; i++) {
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miscRegFile[per_tc_regs[i]].resize(num_threads);
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bankType[per_tc_regs[i]] = perThreadContext;
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}
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if (num_vpes > 1) {
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for (int i=1; i < num_vpes; i++) {
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clear(i);
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}
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}
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}
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//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
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2009-07-09 08:02:20 +02:00
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void
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2009-07-10 05:28:39 +02:00
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ISA::reset(std::string core_name, ThreadID num_threads,
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unsigned num_vpes, BaseCPU *_cpu)
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{
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DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
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num_threads, num_vpes);
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cpu = _cpu;
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MipsISA::CoreSpecific &cp = cpu->coreParams;
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// Do Default CP0 initialization HERE
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// Do Initialization for MT cores here (eventually use
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// core_name parameter to toggle this initialization)
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// ===================================================
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DPRINTF(MipsPRA, "Initializing CP0 State.... ");
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MiscReg ProcID = readMiscRegNoEffect(PRId);
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replaceBits(ProcID,PRIdCoOp_HI,PRIdCoOp_LO,cp.CP0_PRId_CompanyOptions);
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replaceBits(ProcID,PRIdCoID_HI,PRIdCoID_LO,cp.CP0_PRId_CompanyID);
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replaceBits(ProcID,PRIdProc_ID_HI,PRIdProc_ID_LO,cp.CP0_PRId_ProcessorID);
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replaceBits(ProcID,PRIdRev_HI,PRIdRev_LO,cp.CP0_PRId_Revision);
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setMiscRegNoEffect(PRId,ProcID);
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// Now, create Write Mask for ProcID register
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MiscReg ProcID_Mask = 0; // Read-Only register
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replaceBits(ProcID_Mask,0,32,0);
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setRegMask(PRId,ProcID_Mask);
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// Config
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MiscReg cfg = readMiscRegNoEffect(Config);
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replaceBits(cfg, Config_BE_HI, Config_BE_LO, cp.CP0_Config_BE);
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replaceBits(cfg, Config_AT_HI, Config_AT_LO, cp.CP0_Config_AT);
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replaceBits(cfg, Config_AR_HI, Config_AR_LO, cp.CP0_Config_AR);
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replaceBits(cfg, Config_MT_HI, Config_MT_LO, cp.CP0_Config_MT);
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replaceBits(cfg, Config_VI_HI, Config_VI_LO, cp.CP0_Config_VI);
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replaceBits(cfg, Config_M, 1);
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setMiscRegNoEffect(Config, cfg);
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// Now, create Write Mask for Config register
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MiscReg cfg_Mask = 0x7FFF0007;
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replaceBits(cfg_Mask,0,32,0);
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setRegMask(Config,cfg_Mask);
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// Config1
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MiscReg cfg1 = readMiscRegNoEffect(Config1);
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replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO,
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cp.CP0_Config1_MMU);
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replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, cp.CP0_Config1_IS);
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replaceBits(cfg1, Config1_IL_HI, Config1_IL_LO, cp.CP0_Config1_IL);
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replaceBits(cfg1, Config1_IA_HI, Config1_IA_LO, cp.CP0_Config1_IA);
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replaceBits(cfg1, Config1_DS_HI, Config1_DS_LO, cp.CP0_Config1_DS);
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replaceBits(cfg1, Config1_DL_HI, Config1_DL_LO, cp.CP0_Config1_DL);
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replaceBits(cfg1, Config1_DA_HI, Config1_DA_LO, cp.CP0_Config1_DA);
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replaceBits(cfg1, Config1_FP_HI, Config1_FP_LO, cp.CP0_Config1_FP);
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replaceBits(cfg1, Config1_EP_HI, Config1_EP_LO, cp.CP0_Config1_EP);
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replaceBits(cfg1, Config1_WR_HI, Config1_WR_LO, cp.CP0_Config1_WR);
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replaceBits(cfg1, Config1_MD_HI, Config1_MD_LO, cp.CP0_Config1_MD);
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replaceBits(cfg1, Config1_C2_HI, Config1_C2_LO, cp.CP0_Config1_C2);
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replaceBits(cfg1, Config1_PC_HI, Config1_PC_LO, cp.CP0_Config1_PC);
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replaceBits(cfg1, Config1_M, cp.CP0_Config1_M);
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setMiscRegNoEffect(Config1, cfg1);
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// Now, create Write Mask for Config register
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MiscReg cfg1_Mask = 0; // Read Only Register
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replaceBits(cfg1_Mask,0,32,0);
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setRegMask(Config1,cfg1_Mask);
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// Config2
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MiscReg cfg2 = readMiscRegNoEffect(Config2);
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replaceBits(cfg2, Config2_TU_HI, Config2_TU_LO, cp.CP0_Config2_TU);
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replaceBits(cfg2, Config2_TS_HI, Config2_TS_LO, cp.CP0_Config2_TS);
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replaceBits(cfg2, Config2_TL_HI, Config2_TL_LO, cp.CP0_Config2_TL);
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replaceBits(cfg2, Config2_TA_HI, Config2_TA_LO, cp.CP0_Config2_TA);
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replaceBits(cfg2, Config2_SU_HI, Config2_SU_LO, cp.CP0_Config2_SU);
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replaceBits(cfg2, Config2_SS_HI, Config2_SS_LO, cp.CP0_Config2_SS);
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replaceBits(cfg2, Config2_SL_HI, Config2_SL_LO, cp.CP0_Config2_SL);
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replaceBits(cfg2, Config2_SA_HI, Config2_SA_LO, cp.CP0_Config2_SA);
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replaceBits(cfg2, Config2_M, cp.CP0_Config2_M);
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setMiscRegNoEffect(Config2, cfg2);
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// Now, create Write Mask for Config register
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MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
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replaceBits(cfg2_Mask,0,32,0);
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setRegMask(Config2,cfg2_Mask);
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// Config3
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MiscReg cfg3 = readMiscRegNoEffect(Config3);
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replaceBits(cfg3, Config3_DSPP_HI, Config3_DSPP_LO, cp.CP0_Config3_DSPP);
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replaceBits(cfg3, Config3_LPA_HI, Config3_LPA_LO, cp.CP0_Config3_LPA);
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replaceBits(cfg3, Config3_VEIC_HI, Config3_VEIC_LO, cp.CP0_Config3_VEIC);
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replaceBits(cfg3, Config3_VINT_HI, Config3_VINT_LO, cp.CP0_Config3_VInt);
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replaceBits(cfg3, Config3_SP_HI, Config3_SP_LO, cp.CP0_Config3_SP);
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replaceBits(cfg3, Config3_MT_HI, Config3_MT_LO, cp.CP0_Config3_MT);
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replaceBits(cfg3, Config3_SM_HI, Config3_SM_LO, cp.CP0_Config3_SM);
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replaceBits(cfg3, Config3_TL_HI, Config3_TL_LO, cp.CP0_Config3_TL);
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setMiscRegNoEffect(Config3, cfg3);
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// Now, create Write Mask for Config register
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MiscReg cfg3_Mask = 0; // Read Only Register
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replaceBits(cfg3_Mask,0,32,0);
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setRegMask(Config3,cfg3_Mask);
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// EBase - CPUNum
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MiscReg EB = readMiscRegNoEffect(EBase);
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replaceBits(EB, EBase_CPUNum_HI, EBase_CPUNum_LO, cp.CP0_EBase_CPUNum);
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replaceBits(EB, 31, 31, 1);
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setMiscRegNoEffect(EBase, EB);
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// Now, create Write Mask for Config register
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MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
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// entire register is read only
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replaceBits(EB_Mask,0,32,0);
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setRegMask(EBase,EB_Mask);
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// SRS Control - HSS (Highest Shadow Set)
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MiscReg SC = readMiscRegNoEffect(SRSCtl);
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replaceBits(SC, SRSCtl_HSS_HI,SRSCtl_HSS_LO,cp.CP0_SrsCtl_HSS);
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setMiscRegNoEffect(SRSCtl, SC);
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// Now, create Write Mask for the SRS Ctl register
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MiscReg SC_Mask = 0x0000F3C0;
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replaceBits(SC_Mask,0,32,0);
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setRegMask(SRSCtl,SC_Mask);
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// IntCtl - IPTI, IPPCI
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MiscReg IC = readMiscRegNoEffect(IntCtl);
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replaceBits(IC, IntCtl_IPTI_HI,IntCtl_IPTI_LO,cp.CP0_IntCtl_IPTI);
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replaceBits(IC, IntCtl_IPPCI_HI,IntCtl_IPPCI_LO,cp.CP0_IntCtl_IPPCI);
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setMiscRegNoEffect(IntCtl, IC);
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// Now, create Write Mask for the IntCtl register
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MiscReg IC_Mask = 0x000003E0;
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replaceBits(IC_Mask,0,32,0);
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setRegMask(IntCtl,IC_Mask);
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// Watch Hi - M - FIXME (More than 1 Watch register)
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MiscReg WHi = readMiscRegNoEffect(WatchHi0);
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replaceBits(WHi, WatchHi_M, cp.CP0_WatchHi_M);
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setMiscRegNoEffect(WatchHi0, WHi);
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// Now, create Write Mask for the IntCtl register
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|
MiscReg wh_Mask = 0x7FFF0FFF;
|
|
|
|
replaceBits(wh_Mask,0,32,0);
|
|
|
|
setRegMask(WatchHi0,wh_Mask);
|
|
|
|
|
|
|
|
// Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
|
|
|
|
MiscReg PCtr = readMiscRegNoEffect(PerfCnt0);
|
|
|
|
replaceBits(PCtr, PerfCntCtl_M, cp.CP0_PerfCtr_M);
|
|
|
|
replaceBits(PCtr, PerfCntCtl_W, cp.CP0_PerfCtr_W);
|
|
|
|
setMiscRegNoEffect(PerfCnt0, PCtr);
|
|
|
|
// Now, create Write Mask for the IntCtl register
|
|
|
|
MiscReg pc_Mask = 0x00007FF;
|
|
|
|
replaceBits(pc_Mask,0,32,0);
|
|
|
|
setRegMask(PerfCnt0,pc_Mask);
|
|
|
|
|
|
|
|
// Random
|
|
|
|
MiscReg random = readMiscRegNoEffect(CP0_Random);
|
|
|
|
random = 63;
|
|
|
|
setMiscRegNoEffect(CP0_Random, random);
|
|
|
|
// Now, create Write Mask for the IntCtl register
|
|
|
|
MiscReg random_Mask = 0;
|
|
|
|
replaceBits(random_Mask,0,32,0);
|
|
|
|
setRegMask(CP0_Random,random_Mask);
|
|
|
|
|
|
|
|
// PageGrain
|
|
|
|
MiscReg pagegrain = readMiscRegNoEffect(PageGrain);
|
|
|
|
replaceBits(pagegrain,PageGrain_ESP,cp.CP0_Config3_SP);
|
|
|
|
setMiscRegNoEffect(PageGrain, pagegrain);
|
|
|
|
// Now, create Write Mask for the IntCtl register
|
|
|
|
MiscReg pg_Mask = 0x10000000;
|
|
|
|
replaceBits(pg_Mask,0,32,0);
|
|
|
|
setRegMask(PageGrain,pg_Mask);
|
|
|
|
|
|
|
|
// Status
|
|
|
|
MiscReg stat = readMiscRegNoEffect(Status);
|
|
|
|
// Only CU0 and IE are modified on a reset - everything else needs
|
|
|
|
// to be controlled on a per CPU model basis
|
|
|
|
|
|
|
|
// Enable CP0 on reset
|
|
|
|
// replaceBits(stat, Status_CU0_HI,Status_CU0_LO, 1);
|
|
|
|
|
|
|
|
// Enable ERL bit on a reset
|
|
|
|
replaceBits(stat, Status_ERL_HI, Status_ERL_LO, 1);
|
|
|
|
|
|
|
|
// Enable BEV bit on a reset
|
|
|
|
replaceBits(stat, Status_BEV_HI, Status_BEV_LO, 1);
|
|
|
|
|
|
|
|
setMiscRegNoEffect(Status, stat);
|
|
|
|
// Now, create Write Mask for the Status register
|
|
|
|
MiscReg stat_Mask = 0xFF78FF17;
|
|
|
|
replaceBits(stat_Mask,0,32,0);
|
|
|
|
setRegMask(Status,stat_Mask);
|
|
|
|
|
|
|
|
|
|
|
|
// MVPConf0
|
|
|
|
MiscReg mvp_conf0 = readMiscRegNoEffect(MVPConf0);
|
|
|
|
replaceBits(mvp_conf0, MVPC0_TCA, 1);
|
|
|
|
replaceBits(mvp_conf0, MVPC0_PVPE_HI, MVPC0_PVPE_LO, num_vpes - 1);
|
|
|
|
replaceBits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO, num_threads - 1);
|
|
|
|
setMiscRegNoEffect(MVPConf0, mvp_conf0);
|
|
|
|
|
|
|
|
// VPEConf0
|
|
|
|
MiscReg vpe_conf0 = readMiscRegNoEffect(VPEConf0);
|
|
|
|
replaceBits(vpe_conf0, VPEC0_MVP, 1);
|
|
|
|
setMiscRegNoEffect(VPEConf0, vpe_conf0);
|
|
|
|
|
|
|
|
// TCBind
|
|
|
|
for (ThreadID tid = 0; tid < num_threads; tid++) {
|
|
|
|
MiscReg tc_bind = readMiscRegNoEffect(TCBind, tid);
|
|
|
|
replaceBits(tc_bind, TCB_CUR_TC_HI, TCB_CUR_TC_LO, tid);
|
|
|
|
setMiscRegNoEffect(TCBind, tc_bind, tid);
|
|
|
|
}
|
|
|
|
// TCHalt
|
|
|
|
MiscReg tc_halt = readMiscRegNoEffect(TCHalt);
|
|
|
|
replaceBits(tc_halt, TCH_H, 0);
|
|
|
|
setMiscRegNoEffect(TCHalt, tc_halt);
|
|
|
|
/*for (ThreadID tid = 1; tid < num_threads; tid++) {
|
|
|
|
// Set TCHalt Halt bit to 1 for all other threads
|
|
|
|
tc_halt = readMiscRegNoEffect(TCHalt, tid);
|
|
|
|
replaceBits(tc_halt, TCH_H, 1);
|
|
|
|
setReg(TCHalt, tc_halt, tid);
|
|
|
|
}*/
|
|
|
|
|
|
|
|
// TCStatus
|
|
|
|
// Set TCStatus Activated to 1 for the initial thread that is running
|
|
|
|
MiscReg tc_status = readMiscRegNoEffect(TCStatus);
|
|
|
|
replaceBits(tc_status, TCS_A, 1);
|
|
|
|
setMiscRegNoEffect(TCStatus, tc_status);
|
|
|
|
|
|
|
|
// Set Dynamically Allocatable bit to 1 for all other threads
|
|
|
|
for (ThreadID tid = 1; tid < num_threads; tid++) {
|
|
|
|
tc_status = readMiscRegNoEffect(TCStatus, tid);
|
|
|
|
replaceBits(tc_status, TCSTATUS_DA, 1);
|
|
|
|
setMiscRegNoEffect(TCStatus, tc_status, tid);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
MiscReg Mask = 0x7FFFFFFF;
|
|
|
|
|
|
|
|
// Now, create Write Mask for the Index register
|
|
|
|
replaceBits(Mask,0,32,0);
|
|
|
|
setRegMask(Index,Mask);
|
|
|
|
|
|
|
|
Mask = 0x3FFFFFFF;
|
|
|
|
replaceBits(Mask,0,32,0);
|
|
|
|
setRegMask(EntryLo0,Mask);
|
|
|
|
setRegMask(EntryLo1,Mask);
|
|
|
|
|
|
|
|
Mask = 0xFF800000;
|
|
|
|
replaceBits(Mask,0,32,0);
|
|
|
|
setRegMask(Context,Mask);
|
|
|
|
|
|
|
|
Mask = 0x1FFFF800;
|
|
|
|
replaceBits(Mask,0,32,0);
|
|
|
|
setRegMask(PageMask,Mask);
|
|
|
|
|
|
|
|
Mask = 0x0;
|
|
|
|
replaceBits(Mask,0,32,0);
|
|
|
|
setRegMask(BadVAddr,Mask);
|
|
|
|
setRegMask(LLAddr,Mask);
|
|
|
|
|
|
|
|
Mask = 0x08C00300;
|
|
|
|
replaceBits(Mask,0,32,0);
|
|
|
|
setRegMask(Cause,Mask);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
inline unsigned
|
|
|
|
ISA::getVPENum(ThreadID tid)
|
2009-07-09 08:02:20 +02:00
|
|
|
{
|
2009-07-10 05:28:39 +02:00
|
|
|
unsigned tc_bind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid];
|
|
|
|
return bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
|
2009-07-09 08:02:20 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
MiscReg
|
2009-07-10 05:28:39 +02:00
|
|
|
ISA::readMiscRegNoEffect(int reg_idx, ThreadID tid)
|
|
|
|
{
|
|
|
|
int misc_reg = reg_idx - Ctrl_Base_DepTag;
|
|
|
|
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
|
|
|
|
? tid : getVPENum(tid);
|
|
|
|
DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
|
|
|
|
misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
|
|
|
|
miscRegFile[misc_reg][reg_sel]);
|
|
|
|
return miscRegFile[misc_reg][reg_sel];
|
|
|
|
}
|
|
|
|
|
|
|
|
//@TODO: MIPS MT's register view automatically connects
|
|
|
|
// Status to TCStatus depending on current thread
|
|
|
|
//template <class TC>
|
|
|
|
MiscReg
|
|
|
|
ISA::readMiscReg(int reg_idx, ThreadContext *tc, ThreadID tid)
|
|
|
|
{
|
|
|
|
int misc_reg = reg_idx - Ctrl_Base_DepTag;
|
|
|
|
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
|
|
|
|
? tid : getVPENum(tid);
|
|
|
|
DPRINTF(MipsPRA,
|
|
|
|
"Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
|
|
|
|
misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
|
|
|
|
miscRegFile[misc_reg][reg_sel]);
|
|
|
|
|
|
|
|
|
|
|
|
switch (misc_reg)
|
|
|
|
{
|
|
|
|
default:
|
|
|
|
return miscRegFile[misc_reg][reg_sel];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
ISA::setMiscRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid)
|
|
|
|
{
|
|
|
|
int misc_reg = reg_idx - Ctrl_Base_DepTag;
|
|
|
|
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
|
|
|
|
? tid : getVPENum(tid);
|
|
|
|
DPRINTF(MipsPRA,
|
|
|
|
"[tid:%i]: Setting (direct set) CP0 Register:%u "
|
|
|
|
"Select:%u (%s) to %#x.\n",
|
|
|
|
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
|
|
|
|
|
|
|
|
miscRegFile[misc_reg][reg_sel] = val;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
ISA::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid)
|
2009-07-09 08:02:20 +02:00
|
|
|
{
|
2009-07-10 05:28:39 +02:00
|
|
|
// return;
|
|
|
|
int misc_reg = reg_idx - Ctrl_Base_DepTag;
|
|
|
|
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
|
|
|
|
? tid : getVPENum(tid);
|
|
|
|
DPRINTF(MipsPRA,
|
|
|
|
"[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
|
|
|
|
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
|
|
|
|
miscRegFile_WriteMask[misc_reg][reg_sel] = val;
|
2009-07-09 08:02:20 +02:00
|
|
|
}
|
|
|
|
|
2009-07-10 05:28:39 +02:00
|
|
|
// PROGRAMMER'S NOTES:
|
|
|
|
// (1) Some CP0 Registers have fields that cannot
|
|
|
|
// be overwritten. Make sure to handle those particular registers
|
|
|
|
// with care!
|
|
|
|
//template <class TC>
|
|
|
|
void
|
|
|
|
ISA::setMiscReg(int reg_idx, const MiscReg &val,
|
|
|
|
ThreadContext *tc, ThreadID tid)
|
|
|
|
{
|
|
|
|
int misc_reg = reg_idx - Ctrl_Base_DepTag;
|
|
|
|
int reg_sel = (bankType[misc_reg] == perThreadContext)
|
|
|
|
? tid : getVPENum(tid);
|
|
|
|
|
|
|
|
DPRINTF(MipsPRA,
|
|
|
|
"[tid:%i]: Setting CP0 Register:%u "
|
|
|
|
"Select:%u (%s) to %#x, with effect.\n",
|
|
|
|
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
|
|
|
|
|
|
|
|
MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
|
|
|
|
|
|
|
|
miscRegFile[misc_reg][reg_sel] = cp0_val;
|
|
|
|
|
|
|
|
scheduleCP0Update(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* This method doesn't need to adjust the Control Register Offset
|
|
|
|
* since it has already been done in the calling method
|
|
|
|
* (setRegWithEffect)
|
|
|
|
*/
|
2009-07-09 08:02:20 +02:00
|
|
|
MiscReg
|
2009-07-10 05:28:39 +02:00
|
|
|
ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
|
|
|
|
{
|
|
|
|
MiscReg retVal = val;
|
|
|
|
|
|
|
|
// Mask off read-only regions
|
|
|
|
retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
|
|
|
|
MiscReg curVal = miscRegFile[misc_reg][reg_sel];
|
|
|
|
// Mask off current alue with inverse mask (clear writeable bits)
|
|
|
|
curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
|
|
|
|
retVal |= curVal; // Combine the two
|
|
|
|
DPRINTF(MipsPRA,
|
|
|
|
"filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
|
|
|
|
"current val: %lx, written val: %x\n",
|
|
|
|
miscRegFile_WriteMask[misc_reg][reg_sel],
|
|
|
|
~miscRegFile_WriteMask[misc_reg][reg_sel],
|
|
|
|
val, miscRegFile[misc_reg][reg_sel], retVal);
|
|
|
|
return retVal;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
ISA::scheduleCP0Update(int delay)
|
2009-07-09 08:02:20 +02:00
|
|
|
{
|
2009-07-10 05:28:39 +02:00
|
|
|
if (!cp0Updated) {
|
|
|
|
cp0Updated = true;
|
|
|
|
|
|
|
|
//schedule UPDATE
|
|
|
|
CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
|
|
|
|
cpu->schedule(cp0_event, curTick + cpu->ticks(delay));
|
|
|
|
}
|
2009-07-09 08:02:20 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-07-10 05:28:39 +02:00
|
|
|
ISA::updateCPU()
|
2009-07-09 08:02:20 +02:00
|
|
|
{
|
2009-07-10 05:28:39 +02:00
|
|
|
///////////////////////////////////////////////////////////////////
|
|
|
|
//
|
|
|
|
// EVALUATE CP0 STATE FOR MIPS MT
|
|
|
|
//
|
|
|
|
///////////////////////////////////////////////////////////////////
|
|
|
|
unsigned mvp_conf0 = readMiscRegNoEffect(MVPConf0);
|
|
|
|
ThreadID num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
|
|
|
|
|
|
|
|
for (ThreadID tid = 0; tid < num_threads; tid++) {
|
|
|
|
MiscReg tc_status = readMiscRegNoEffect(TCStatus, tid);
|
|
|
|
MiscReg tc_halt = readMiscRegNoEffect(TCHalt, tid);
|
|
|
|
|
|
|
|
//@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
|
|
|
|
if (bits(tc_halt, TCH_H) == 1 || bits(tc_status, TCS_A) == 0) {
|
|
|
|
haltThread(cpu->getContext(tid));
|
|
|
|
} else if (bits(tc_halt, TCH_H) == 0 && bits(tc_status, TCS_A) == 1) {
|
|
|
|
restoreThread(cpu->getContext(tid));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
|
|
|
|
|
|
|
|
// Toggle update flag after we finished updating
|
|
|
|
cp0Updated = false;
|
2009-07-09 08:02:20 +02:00
|
|
|
}
|
|
|
|
|
2009-07-10 05:28:39 +02:00
|
|
|
ISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type)
|
|
|
|
: Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type)
|
|
|
|
{ }
|
|
|
|
|
2009-07-09 08:02:20 +02:00
|
|
|
void
|
2009-07-10 05:28:39 +02:00
|
|
|
ISA::CP0Event::process()
|
|
|
|
{
|
|
|
|
switch (cp0EventType)
|
|
|
|
{
|
|
|
|
case UpdateCP0:
|
|
|
|
cp0->updateCPU();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
//cp0EventRemoveList.push(this);
|
|
|
|
}
|
|
|
|
|
|
|
|
const char *
|
|
|
|
ISA::CP0Event::description() const
|
2009-07-09 08:02:20 +02:00
|
|
|
{
|
2009-07-10 05:28:39 +02:00
|
|
|
return "Coprocessor-0 event";
|
2009-07-09 08:02:20 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-07-10 05:28:39 +02:00
|
|
|
ISA::CP0Event::scheduleEvent(int delay)
|
2009-07-09 08:02:20 +02:00
|
|
|
{
|
2009-07-10 05:28:39 +02:00
|
|
|
cpu->reschedule(this, curTick + cpu->ticks(delay), true);
|
2009-07-09 08:02:20 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2009-07-10 05:28:39 +02:00
|
|
|
ISA::CP0Event::unscheduleEvent()
|
2009-07-09 08:02:20 +02:00
|
|
|
{
|
2009-07-10 05:28:39 +02:00
|
|
|
if (scheduled())
|
|
|
|
squash();
|
2009-07-09 08:02:20 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
}
|