2005-01-15 10:12:25 +01:00
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simobj BaseCPU(SimObject):
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2005-02-03 03:13:01 +01:00
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type = 'BaseCPU'
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2005-01-15 10:12:25 +01:00
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abstract = True
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icache = Param.BaseMem(NULL, "L1 instruction cache object")
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dcache = Param.BaseMem(NULL, "L1 data cache object")
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2005-03-09 20:42:30 +01:00
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if Bool._convert(env.get('FULL_SYSTEM', 'False')):
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dtb = Param.AlphaDTB("Data TLB")
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itb = Param.AlphaITB("Instruction TLB")
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mem = Param.FunctionalMemory("memory")
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system = Param.BaseSystem(Super, "system object")
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else:
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workload = VectorParam.Process("processes to run")
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2005-01-15 10:12:25 +01:00
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max_insts_all_threads = Param.Counter(0,
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"terminate when all threads have reached this inst count")
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max_insts_any_thread = Param.Counter(0,
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"terminate when any thread reaches this inst count")
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max_loads_all_threads = Param.Counter(0,
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"terminate when all threads have reached this load count")
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max_loads_any_thread = Param.Counter(0,
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"terminate when any thread reaches this load count")
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2005-02-03 23:04:54 +01:00
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defer_registration = Param.Bool(False,
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2005-01-15 10:12:25 +01:00
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"defer registration with system (for sampling)")
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