200 lines
7.4 KiB
Python
200 lines
7.4 KiB
Python
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# Copyright (c)2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Curtis Dunham
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import sst
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import sys
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import os
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lat="1 ns"
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buslat="2 ns"
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clockRate = "1GHz"
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def getenv(name):
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res = ""
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try:
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res = os.environ[name]
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except KeyError:
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pass
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return res
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baseCacheParams = ({
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"debug" :getenv("DEBUG"),
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"debug_level" : 6,
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"coherence_protocol" : "MSI",
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"replacement_policy" : "LRU",
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"cache_line_size" : 64,
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"cache_frequency" : clockRate,
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"statistics" : 1
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})
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l1CacheParams = ({
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"debug" : getenv("DEBUG"),
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"debug_level" : 6,
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"L1" : 1,
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"cache_size" : "64 KB",
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"associativity" : 4,
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"access_latency_cycles" : 2,
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"low_network_links" : 1
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})
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l2CacheParams = ({
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"debug" : getenv("DEBUG"),
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"debug_level" : 6,
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"L1" : 0,
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"cache_size" : "256 KB",
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"associativity" : 8,
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"access_latency_cycles" : 8,
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"high_network_links" : 1,
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"mshr_num_entries" : 4096,
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"low_network_links" : 1
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})
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GEM5 = sst.Component("system", "gem5.gem5")
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GEM5.addParams({
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"comp_debug" : getenv("GEM5_DEBUG"),
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"gem5DebugFlags" : getenv("M5_DEBUG"),
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"frequency" : clockRate,
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"cmd" : "configs/example/fs.py --num-cpus 4 --disk-image=vexpress64-openembedded_minimal-armv8_20130623-376.img --root-device=/dev/sda2 --kernel=vmlinux.aarch64.20140821 --dtb-filename=vexpress.aarch64.20140821.dtb --mem-size=256MB --machine-type=VExpress_EMM64 --cpu-type=timing --external-memory-system=sst --initialize-only"
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})
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bus = sst.Component("membus", "memHierarchy.Bus")
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bus.addParams({
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"bus_frequency": "2GHz",
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"debug" : getenv("DEBUG"),
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"debug_level" : 8
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})
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def buildL1(name, m5, connector):
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cache = sst.Component(name, "memHierarchy.Cache")
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cache.addParams(baseCacheParams)
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cache.addParams(l1CacheParams)
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link = sst.Link("cpu_%s_link"%name)
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link.connect((m5, connector, lat), (cache, "high_network_0", lat))
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return cache
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SysBusConn = buildL1("gem5SystemBus", GEM5, "system.external_memory.port")
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bus_port = 0
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link = sst.Link("sysbus_bus_link")
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link.connect((SysBusConn, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
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bus_port = bus_port + 1
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ioCache = buildL1("ioCache", GEM5, "system.iocache.port")
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ioCache.addParams({
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"debug" : 0,
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"debug_level" : 6,
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"cache_size" : "16 KB",
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"associativity" : 4
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})
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link = sst.Link("ioCache_bus_link")
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link.connect((ioCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
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def buildCPU(m5, num):
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l1iCache = buildL1("cpu%u.l1iCache" % num, m5, "system.cpu%u.icache.port" % num)
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l1dCache = buildL1("cpu%u.l1dCache" % num, m5, "system.cpu%u.dcache.port" % num)
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itlbCache = buildL1("cpu%u.itlbCache" % num, m5, "system.cpu%u.itb_walker_cache.port" % num)
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dtlbCache = buildL1("cpu%u.dtlbCache" % num, m5, "system.cpu%u.dtb_walker_cache.port" % num)
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l1dCache.addParams({
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"debug" : 0,
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"debug_level" : 10,
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"snoop_l1_invalidations" : 1
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})
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global bus_port
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link = sst.Link("cpu%u.l1iCache_bus_link" % num) ; bus_port = bus_port + 1
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link.connect((l1iCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
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link = sst.Link("cpu%u.l1dCache_bus_link" % num) ; bus_port = bus_port + 1
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link.connect((l1dCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
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link = sst.Link("cpu%u.itlbCache_bus_link" % num) ; bus_port = bus_port + 1
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link.connect((itlbCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
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link = sst.Link("cpu%u.dtlbCache_bus_link" % num) ; bus_port = bus_port + 1
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link.connect((dtlbCache, "low_network_0", buslat), (bus, "high_network_%u" % bus_port, buslat))
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buildCPU(GEM5, 0)
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buildCPU(GEM5, 1)
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buildCPU(GEM5, 2)
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buildCPU(GEM5, 3)
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l2cache = sst.Component("l2cache", "memHierarchy.Cache")
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l2cache.addParams(baseCacheParams)
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l2cache.addParams(l2CacheParams)
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l2cache.addParams({
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"network_address" : "2",
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"directory_at_next_level" : "1"
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})
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link = sst.Link("l2cache_bus_link")
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link.connect((l2cache, "high_network_0", buslat), (bus, "low_network_0", buslat))
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memory = sst.Component("memory", "memHierarchy.MemController")
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memory.addParams({
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"request_width" : 64,
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"coherence_protocol" : "MSI",
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"access_time" : "25 ns",
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"backend.mem_size" : 256,
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"clock" : "2GHz",
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"debug" : getenv("DEBUG"),
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"range_start" : 0, # 2 * (1024 ** 3), # it's behind a directory controller.
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})
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comp_chiprtr = sst.Component("chiprtr", "merlin.hr_router")
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comp_chiprtr.addParams({
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"xbar_bw" : "16GB/s",
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"link_bw" : "16GB/s",
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"input_buf_size" : "1KB",
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"num_ports" : "3",
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"flit_size" : "72B",
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"output_buf_size" : "1KB",
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"id" : "0",
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"topology" : "merlin.singlerouter"
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})
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comp_dirctrl = sst.Component("dirctrl", "memHierarchy.DirectoryController")
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comp_dirctrl.addParams({
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"coherence_protocol" : "MSI",
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"network_address" : "1",
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"entry_cache_size" : "16384",
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"network_bw" : "1GB/s",
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"addr_range_start" : 2 * (1024 ** 3),
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"addr_range_end" : 2 * (1024 ** 3) + 256 * (1024 ** 2)
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})
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sst.Link("link_cache_net_0").connect((l2cache, "directory", "10ns"), (comp_chiprtr, "port2", "2ns"))
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sst.Link("link_dir_net_0").connect((comp_chiprtr, "port1", "2ns"), (comp_dirctrl, "network", "2ns"))
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sst.Link("l2cache_io_link").connect((comp_chiprtr, "port0", "2ns"), (GEM5, "network", buslat))
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sst.Link("link_dir_mem_link").connect((comp_dirctrl, "memory", "10ns"), (memory, "direct_link", "10ns"))
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