2006-01-29 23:25:54 +01:00
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////////////////////////////////////////////////////////////////////
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//
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// Base class for sparc instructions, and some support functions
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//
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output header {{
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2006-03-07 10:33:10 +01:00
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2006-03-17 20:02:38 +01:00
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union CondCodes
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2006-03-07 10:33:10 +01:00
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{
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struct
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{
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uint8_t c:1;
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uint8_t v:1;
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uint8_t z:1;
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uint8_t n:1;
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};
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uint32_t bits;
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};
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enum CondTest
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{
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Always=0x8,
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Never=0x0,
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NotEqual=0x9,
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Equal=0x1,
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Greater=0xA,
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LessOrEqual=0x2,
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GreaterOrEqual=0xB,
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Less=0x3,
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GreaterUnsigned=0xC,
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LessOrEqualUnsigned=0x4,
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CarryClear=0xD,
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CarrySet=0x5,
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Positive=0xE,
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Negative=0x6,
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OverflowClear=0xF,
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OverflowSet=0x7
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};
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2006-01-29 23:25:54 +01:00
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/**
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* Base class for all SPARC static instructions.
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*/
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class SparcStaticInst : public StaticInst
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{
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protected:
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// Constructor.
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SparcStaticInst(const char *mnem,
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MachInst _machInst, OpClass __opClass)
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: StaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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void printReg(std::ostream &os, int reg) const;
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2006-01-29 23:25:54 +01:00
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};
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bool passesCondition(uint32_t codes, uint32_t condition);
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}};
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def template ROrImmDecode {{
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{
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return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst))
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: (SparcStaticInst *)(new %(class_name)s(machInst)));
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}
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}};
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let {{
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def splitOutImm(code):
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matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>d{0,2})')
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rOrImmMatch = matcher.search(code)
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if (rOrImmMatch == None):
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return (False, CodeBlock(code), None, '', '')
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rString = matcher.sub(r'(?P=rNum)', rOrImmMatch.string)
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iString = matcher.sub(r'(?P=iNum)', rOrImmMatch.string)
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orig_code = code
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code = matcher.sub(r'Rs(?P<rNum>)', orig_code)
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imm_code = matcher.sub('imm', orig_code)
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return (True, CodeBlock(code), CodeBlock(imm_code), rString, iString)
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}};
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output decoder {{
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2006-03-16 19:58:50 +01:00
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void
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SparcStaticInst::printReg(std::ostream &os, int reg) const
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{
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if (reg < FP_Base_DepTag) {
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ccprintf(os, "r%d", reg);
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}
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else {
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ccprintf(os, "f%d", reg - FP_Base_DepTag);
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}
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}
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std::string SparcStaticInst::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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// just print the first two source regs... if there's
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// a third one, it's a read-modify-write dest (Rc),
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// e.g. for CMOVxx
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if(_numSrcRegs > 0)
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{
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printReg(ss, _srcRegIdx[0]);
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}
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if(_numSrcRegs > 1)
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{
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ss << ",";
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printReg(ss, _srcRegIdx[1]);
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}
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2006-03-07 10:33:10 +01:00
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// just print the first dest... if there's a second one,
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// it's generally implicit
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if(_numDestRegs > 0)
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{
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if(_numSrcRegs > 0)
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ss << ",";
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printReg(ss, _destRegIdx[0]);
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}
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return ss.str();
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}
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bool passesCondition(uint32_t codes, uint32_t condition)
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{
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CondCodes condCodes;
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condCodes.bits = codes;
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switch(condition)
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{
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case Always:
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return true;
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case Never:
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return false;
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case NotEqual:
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return !condCodes.z;
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case Equal:
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return condCodes.z;
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case Greater:
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return !(condCodes.z | (condCodes.n ^ condCodes.v));
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case LessOrEqual:
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return condCodes.z | (condCodes.n ^ condCodes.v);
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case GreaterOrEqual:
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return !(condCodes.n ^ condCodes.v);
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case Less:
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return (condCodes.n ^ condCodes.v);
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case GreaterUnsigned:
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return !(condCodes.c | condCodes.z);
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case LessOrEqualUnsigned:
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return (condCodes.c | condCodes.z);
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case CarryClear:
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return !condCodes.c;
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case CarrySet:
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return condCodes.c;
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case Positive:
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return !condCodes.n;
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case Negative:
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return condCodes.n;
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case OverflowClear:
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return !condCodes.v;
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case OverflowSet:
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return condCodes.v;
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}
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panic("Tried testing condition nonexistant "
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"condition code %d", condition);
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}
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}};
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