2007-03-29 19:51:12 +02:00
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---------- Begin Simulation Statistics ----------
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2007-05-16 01:25:35 +02:00
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host_inst_rate 480067 # Simulator instruction rate (inst/s)
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|
|
|
|
host_mem_usage 157016 # Number of bytes of host memory used
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|
|
|
|
host_seconds 283.81 # Real time elapsed on the host
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|
host_tick_rate 698858124 # Simulator tick rate (ticks/s)
|
2007-03-29 19:51:12 +02:00
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|
|
sim_freq 1000000000000 # Frequency of simulated ticks
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|
|
|
|
sim_insts 136246936 # Number of instructions simulated
|
2007-05-16 01:25:35 +02:00
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|
|
sim_seconds 0.198342 # Number of seconds simulated
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|
|
|
|
sim_ticks 198341876000 # Number of ticks simulated
|
2007-03-29 19:51:12 +02:00
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|
|
system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
|
2007-05-16 01:25:35 +02:00
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|
|
system.cpu.dcache.ReadReq_avg_miss_latency 13005.210051 # average ReadReq miss latency
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|
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|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12005.210051 # average ReadReq mshr miss latency
|
2007-03-29 19:51:12 +02:00
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|
|
system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits
|
2007-05-16 01:25:35 +02:00
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|
|
system.cpu.dcache.ReadReq_miss_latency 591594000 # number of ReadReq miss cycles
|
2007-03-29 19:51:12 +02:00
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|
|
system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
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|
system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses
|
2007-05-16 01:25:35 +02:00
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|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 546105000 # number of ReadReq MSHR miss cycles
|
2007-03-29 19:51:12 +02:00
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|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
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|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses
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|
|
|
|
system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
|
2007-05-16 01:25:35 +02:00
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|
|
system.cpu.dcache.SwapReq_avg_miss_latency 12800 # average SwapReq miss latency
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|
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|
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11800 # average SwapReq mshr miss latency
|
2007-03-29 19:51:12 +02:00
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|
|
system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits
|
2007-05-16 01:25:35 +02:00
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|
|
system.cpu.dcache.SwapReq_miss_latency 192000 # number of SwapReq miss cycles
|
2007-03-29 19:51:12 +02:00
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|
|
system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses
|
2007-05-16 01:25:35 +02:00
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|
|
system.cpu.dcache.SwapReq_mshr_miss_latency 177000 # number of SwapReq MSHR miss cycles
|
2007-03-29 19:51:12 +02:00
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|
|
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses
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|
|
|
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system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses
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|
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system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
|
2007-05-16 01:25:35 +02:00
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|
|
system.cpu.dcache.WriteReq_avg_miss_latency 13928.024036 # average WriteReq miss latency
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|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12928.024036 # average WriteReq mshr miss latency
|
2007-03-29 19:51:12 +02:00
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|
|
system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_latency 1464866000 # number of WriteReq miss cycles
|
2007-03-29 19:51:12 +02:00
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|
|
system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses
|
|
|
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|
system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 1359692000 # number of WriteReq MSHR miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses
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|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses
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|
|
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|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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|
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|
|
system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
|
2007-05-16 01:25:35 +02:00
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|
|
system.cpu.dcache.demand_avg_miss_latency 13649.402972 # average overall miss latency
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|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency
|
2007-03-29 19:51:12 +02:00
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|
|
system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.demand_miss_latency 2056460000 # number of demand (read+write) miss cycles
|
2007-03-29 19:51:12 +02:00
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|
|
system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses
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|
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|
system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-05-16 01:25:35 +02:00
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|
|
system.cpu.dcache.demand_mshr_miss_latency 1905797000 # number of demand (read+write) MSHR miss cycles
|
2007-03-29 19:51:12 +02:00
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|
|
system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses
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|
|
|
|
system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses
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|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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|
|
|
|
system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
|
2007-05-16 01:25:35 +02:00
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|
|
system.cpu.dcache.overall_avg_miss_latency 13649.402972 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
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system.cpu.dcache.overall_hits 57944942 # number of overall hits
|
2007-05-16 01:25:35 +02:00
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|
|
system.cpu.dcache.overall_miss_latency 2056460000 # number of overall miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses
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|
|
|
|
system.cpu.dcache.overall_misses 150663 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 1905797000 # number of overall MSHR miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.dcache.replacements 146582 # number of replacements
|
|
|
|
|
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.tagsinuse 4089.719370 # Cycle average of tags in use
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 500116000 # Cycle when the warmup percentage was hit.
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.dcache.writebacks 107279 # number of writebacks
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses)
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 12107.905937 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11107.905937 # average ReadReq mshr miss latency
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_latency 2264469000 # number of ReadReq miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 2077445000 # number of ReadReq MSHR miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_refs 727.499749 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.demand_avg_miss_latency 12107.905937 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.demand_miss_latency 2264469000 # number of demand (read+write) miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_latency 2077445000 # number of demand (read+write) MSHR miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_avg_miss_latency 12107.905937 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.overall_hits 136059913 # number of overall hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_miss_latency 2264469000 # number of overall miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 187024 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_latency 2077445000 # number of overall MSHR miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.icache.replacements 184976 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.tagsinuse 2007.901723 # Cycle average of tags in use
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks.
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.icache.warmup_cycle 141263674000 # Cycle when the warmup percentage was hit.
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
|
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses)
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 12999.502521 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.502521 # average ReadReq mshr miss latency
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1750760000 # number of ReadReq miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1481402000 # number of ReadReq MSHR miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 106771 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_miss_rate 0.004735 # miss rate for Writeback accesses
|
|
|
|
|
system.cpu.l2cache.Writeback_misses 508 # number of Writeback misses
|
|
|
|
|
system.cpu.l2cache.Writeback_mshr_miss_rate 0.004735 # mshr miss rate for Writeback accesses
|
|
|
|
|
system.cpu.l2cache.Writeback_mshr_misses 508 # number of Writeback MSHR misses
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_refs 2.299750 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 12999.502521 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 1750760000 # number of demand (read+write) miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 1481402000 # number of demand (read+write) MSHR miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 12950.653539 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_hits 309728 # number of overall hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 1750760000 # number of overall miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 135187 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 1481402000 # number of overall MSHR miss cycles
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.l2cache.replacements 101911 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 32127.015431 # Cycle average of tags in use
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks.
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 41711518000 # Cycle when the warmup percentage was hit.
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.l2cache.writebacks 82918 # number of writebacks
|
|
|
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
2007-05-16 01:25:35 +02:00
|
|
|
system.cpu.numCycles 198341876000 # number of cpu cycles simulated
|
2007-03-29 19:51:12 +02:00
|
|
|
system.cpu.num_insts 136246936 # Number of instructions executed
|
|
|
|
|
system.cpu.num_refs 58111522 # Number of memory references
|
|
|
|
|
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
