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gem5/tests/configs/o3-timing.py

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config: Add a BaseSESystem builder for re-use in regressions This patch extends the existing system builders to also include a syscall-emulation builder. This builder is deployed in all syscall-emulation regressions that do not involve Ruby, i.e. o3-timing, simple-timing and simple-atomic, as well as the multi-processor regressions o3-timing-mp, simple-timing-mp and simple-atomic-mp (the latter are only used by SPARC at this point). The values chosen for the cache sizes match those that were used in the existing config scripts (despite being on the large side). Similarly, a mem_class parameter is added to the builder base class to enable simple-atomic to use SimpleMemory and o3-timing to use the default DDR3 configuration. Due to the different order the ports are connected, the bus stats get shuffled around for the multi-processor regressions. A separate patch bumps the port indices. Besides this, all behaviour is exactly the same.
2013-06-27 11:49:49 +02:00
# Copyright (c) 2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
A couple of minor fixes. 1. Set CPU ID in all modes for the O3 CPU. 2. Use nextCycle() function to prevent phase drift in O3 CPU. 3. Remove assertion in rename map that is no longer true. src/cpu/o3/alpha/cpu_builder.cc: Allow for CPU id in all modes, not just full system. Also include a parameter that was left out by accident. src/cpu/o3/alpha/cpu_impl.hh: Set the CPU ID properly. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: Use nextCycle() function so that the CPU does not get out of phase when starting up from quiesces. src/cpu/o3/rename_map.cc: Remove assertion that is no longer true. tests/configs/o3-timing.py: Set CPU's id to 0. --HG-- extra : convert_revision : 2b69c19adfce2adcc2d1939e89d702bd6674d5d5
2007-03-23 16:22:43 +01:00
# Copyright (c) 2006-2007 The Regents of The University of Michigan
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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config: Add a BaseSESystem builder for re-use in regressions This patch extends the existing system builders to also include a syscall-emulation builder. This builder is deployed in all syscall-emulation regressions that do not involve Ruby, i.e. o3-timing, simple-timing and simple-atomic, as well as the multi-processor regressions o3-timing-mp, simple-timing-mp and simple-atomic-mp (the latter are only used by SPARC at this point). The values chosen for the cache sizes match those that were used in the existing config scripts (despite being on the large side). Similarly, a mem_class parameter is added to the builder base class to enable simple-atomic to use SimpleMemory and o3-timing to use the default DDR3 configuration. Due to the different order the ports are connected, the bus stats get shuffled around for the multi-processor regressions. A separate patch bumps the port indices. Besides this, all behaviour is exactly the same.
2013-06-27 11:49:49 +02:00
# Authors: Andreas Hansson
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
from m5.objects import *
tests: Use more representative configs for ARM tests This patch changes the CPU and cache configurations used in the ARM SE and FS regressions to make them more representative, and also get better code coverage by exercising different replacement policies and use an L2 prefetcher.
2014-09-20 23:18:33 +02:00
from m5.defines import buildEnv
config: Add a BaseSESystem builder for re-use in regressions This patch extends the existing system builders to also include a syscall-emulation builder. This builder is deployed in all syscall-emulation regressions that do not involve Ruby, i.e. o3-timing, simple-timing and simple-atomic, as well as the multi-processor regressions o3-timing-mp, simple-timing-mp and simple-atomic-mp (the latter are only used by SPARC at this point). The values chosen for the cache sizes match those that were used in the existing config scripts (despite being on the large side). Similarly, a mem_class parameter is added to the builder base class to enable simple-atomic to use SimpleMemory and o3-timing to use the default DDR3 configuration. Due to the different order the ports are connected, the bus stats get shuffled around for the multi-processor regressions. A separate patch bumps the port indices. Besides this, all behaviour is exactly the same.
2013-06-27 11:49:49 +02:00
from base_config import *
tests: Use more representative configs for ARM tests This patch changes the CPU and cache configurations used in the ARM SE and FS regressions to make them more representative, and also get better code coverage by exercising different replacement policies and use an L2 prefetcher.
2014-09-20 23:18:33 +02:00
from arm_generic import *
from O3_ARM_v7a import O3_ARM_v7a_3
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
tests: Use more representative configs for ARM tests This patch changes the CPU and cache configurations used in the ARM SE and FS regressions to make them more representative, and also get better code coverage by exercising different replacement policies and use an L2 prefetcher.
2014-09-20 23:18:33 +02:00
# If we are running ARM regressions, use a more sensible CPU
# configuration. This makes the results more meaningful, and also
# increases the coverage of the regressions.
if buildEnv['TARGET_ISA'] == "arm":
root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
cpu_class=O3_ARM_v7a_3).create_root()
else:
root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
cpu_class=DerivO3CPU).create_root()
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