2010-07-27 07:03:44 +02:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
2011-03-18 01:20:22 +01:00
|
|
|
host_inst_rate 1495798 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 254688 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 233.36 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 909925289 # Simulator tick rate (ticks/s)
|
2010-07-27 07:03:44 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2011-03-18 01:20:22 +01:00
|
|
|
sim_insts 349065408 # Number of instructions simulated
|
|
|
|
|
sim_seconds 0.212344 # Number of seconds simulated
|
|
|
|
|
sim_ticks 212344048000 # Number of ticks simulated
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
2010-11-08 20:59:35 +01:00
|
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.dtb.hits 0 # DTB hits
|
2010-11-08 20:59:35 +01:00
|
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.dtb.misses 0 # DTB misses
|
2010-11-08 20:59:35 +01:00
|
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
2010-11-08 20:59:35 +01:00
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
2010-11-08 20:59:35 +01:00
|
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
2010-11-08 20:59:35 +01:00
|
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.numCycles 424688097 # number of cpu cycles simulated
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.num_busy_cycles 424688097 # Number of busy cycles
|
|
|
|
|
system.cpu.num_conditional_control_insts 16255902 # number of instructions that are conditional controls
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
|
|
|
|
|
system.cpu.num_fp_insts 114216705 # number of float instructions
|
|
|
|
|
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
|
|
|
|
|
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.num_func_calls 12435295 # number of times a function call or return occured
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
2011-03-18 01:20:22 +01:00
|
|
|
system.cpu.num_insts 349065408 # Number of instructions executed
|
|
|
|
|
system.cpu.num_int_alu_accesses 287528428 # Number of integer alu accesses
|
|
|
|
|
system.cpu.num_int_insts 287528428 # number of integer instructions
|
|
|
|
|
system.cpu.num_int_register_reads 1216522338 # number of times the integer registers were read
|
|
|
|
|
system.cpu.num_int_register_writes 216261597 # number of times the integer registers were written
|
|
|
|
|
system.cpu.num_load_insts 94648758 # Number of load instructions
|
|
|
|
|
system.cpu.num_mem_refs 177024357 # number of memory refs
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.num_store_insts 82375599 # Number of store instructions
|
2010-07-27 07:03:44 +02:00
|
|
|
system.cpu.workload.PROG:num_syscalls 191 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
