gem5/src/arch/arm/isa/operands.isa

// -*- mode:c++ -*-

// Copyright (c) 2007-2008 The Florida State University
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// Authors: Stephen Hines

def operand_types {{
    'sb' : ('signed int', 8),
    'ub' : ('unsigned int', 8),
    'sh' : ('signed int', 16),
    'uh' : ('unsigned int', 16),
    'sw' : ('signed int', 32),
    'uw' : ('unsigned int', 32),
    'ud' : ('unsigned int', 64),
    'sf' : ('float', 32),
    'df' : ('float', 64)
}};

let {{
    maybePCRead = '''
        ((%(reg_idx)s == PCReg) ? (xc->readPC() + 8) :
         xc->%(func)s(this, %(op_idx)s))
    '''
    maybePCWrite = '''
        ((%(reg_idx)s == PCReg) ? xc->setNextPC(%(final_val)s) :
         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
    '''
}};

def operands {{
    #General Purpose Integer Reg Operands
    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
    'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
    'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),

    #Destination register for load/store double instructions
    'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
    'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),

    'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 6),
    'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7),
    'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8),
    'LR': ('IntReg', 'uw', '14', 'IsInteger', 9),

    #Register fields for microops
    'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
    'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),

    #General Purpose Floating Point Reg Operands
    'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
    'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
    'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),

    #Memory Operand
    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),

    'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
    'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41),
    'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42),
    'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43),

}};