gem5/src/arch/arm/isa/operands.isa

// -*- mode:c++ -*-

// Copyright (c) 2007-2008 The Florida State University
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// Authors: Stephen Hines

def operand_types {{
    'sb' : ('signed int', 8),
    'ub' : ('unsigned int', 8),
    'sh' : ('signed int', 16),
    'uh' : ('unsigned int', 16),
    'sw' : ('signed int', 32),
    'uw' : ('unsigned int', 32),
    'ud' : ('unsigned int', 64),
    'sf' : ('float', 32),
    'df' : ('float', 64)
}};

def operands {{
    #General Purpose Integer Reg Operands
    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
    'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2),
    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
    'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),

    'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 5),
    'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 5),
    'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 6),
    'LR': ('IntReg', 'uw', '14', 'IsInteger', 6),

    #General Purpose Floating Point Reg Operands
    'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
    'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
    'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 3),

    #Memory Operand
    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),

    'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 7),
    'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 7),
    'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9),
    'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 9),

}};