2006-06-28 17:02:14 +02:00
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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*/
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/**
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* @file
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* Definition of BaseCache functions.
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*/
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2006-10-20 08:38:45 +02:00
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#include "cpu/base.hh"
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#include "cpu/smt.hh"
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2006-06-28 17:02:14 +02:00
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#include "mem/cache/base_cache.hh"
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2006-10-18 06:16:17 +02:00
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#include "mem/cache/miss/mshr.hh"
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2006-06-28 17:02:14 +02:00
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using namespace std;
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2007-05-19 07:35:04 +02:00
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BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache)
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2007-06-18 02:27:53 +02:00
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: SimpleTimingPort(_name, _cache), cache(_cache), otherPort(NULL),
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2007-06-25 15:47:05 +02:00
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blocked(false), mustSendRetry(false)
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2006-06-28 17:02:14 +02:00
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{
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}
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2006-12-14 07:04:36 +01:00
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2007-05-19 07:35:04 +02:00
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BaseCache::BaseCache(const std::string &name, Params ¶ms)
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: MemObject(name),
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2007-06-21 20:59:17 +02:00
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mshrQueue(params.numMSHRs, 4, MSHRQueue_MSHRs),
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writeBuffer(params.numWriteBuffers, params.numMSHRs+1000,
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MSHRQueue_WriteBuffer),
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2007-05-19 07:35:04 +02:00
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blkSize(params.blkSize),
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2007-06-22 18:24:07 +02:00
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hitLatency(params.hitLatency),
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2007-06-18 02:27:53 +02:00
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numTarget(params.numTargets),
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blocked(0),
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noTargetMSHR(NULL),
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missCount(params.maxMisses),
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drainEvent(NULL)
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2007-05-19 07:35:04 +02:00
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{
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}
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2006-06-28 20:35:00 +02:00
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void
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2006-06-28 17:02:14 +02:00
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BaseCache::CachePort::recvStatusChange(Port::Status status)
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{
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2007-05-19 07:35:04 +02:00
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if (status == Port::RangeChange) {
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otherPort->sendStatusChange(Port::RangeChange);
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}
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2006-06-28 17:02:14 +02:00
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}
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int
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BaseCache::CachePort::deviceBlockSize()
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{
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return cache->getBlockSize();
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}
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2006-11-11 04:45:50 +01:00
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void
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BaseCache::CachePort::checkAndSendFunctional(PacketPtr pkt)
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{
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2007-06-18 02:27:53 +02:00
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checkFunctional(pkt);
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2007-06-30 19:16:18 +02:00
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if (!pkt->isResponse())
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2006-11-11 04:45:50 +01:00
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sendFunctional(pkt);
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2006-06-28 17:02:14 +02:00
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}
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2007-05-19 07:35:04 +02:00
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bool
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BaseCache::CachePort::recvRetryCommon()
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{
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assert(waitingOnRetry);
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waitingOnRetry = false;
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return false;
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2006-08-16 21:54:02 +02:00
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}
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2007-05-19 07:35:04 +02:00
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2006-06-28 17:02:14 +02:00
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void
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BaseCache::CachePort::setBlocked()
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{
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2006-08-16 21:54:02 +02:00
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assert(!blocked);
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DPRINTF(Cache, "Cache Blocking\n");
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2006-06-28 17:02:14 +02:00
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blocked = true;
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2006-08-16 21:54:02 +02:00
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//Clear the retry flag
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mustSendRetry = false;
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2006-06-28 17:02:14 +02:00
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}
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void
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BaseCache::CachePort::clearBlocked()
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{
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2006-08-16 21:54:02 +02:00
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assert(blocked);
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DPRINTF(Cache, "Cache Unblocking\n");
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blocked = false;
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2006-08-15 20:24:49 +02:00
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if (mustSendRetry)
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{
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2006-08-16 21:54:02 +02:00
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DPRINTF(Cache, "Cache Sending Retry\n");
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2006-08-15 20:24:49 +02:00
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mustSendRetry = false;
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2007-06-25 15:47:05 +02:00
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SendRetryEvent *ev = new SendRetryEvent(this, true);
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// @TODO: need to find a better time (next bus cycle?)
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ev->schedule(curTick + 1);
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2006-08-15 20:24:49 +02:00
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}
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2006-06-28 17:02:14 +02:00
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}
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2006-07-06 21:15:37 +02:00
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2006-07-07 22:02:22 +02:00
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void
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BaseCache::init()
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{
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if (!cpuSidePort || !memSidePort)
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panic("Cache not hooked up on both sides\n");
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cpuSidePort->sendStatusChange(Port::RangeChange);
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}
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2007-06-21 20:59:17 +02:00
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2006-06-28 17:02:14 +02:00
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void
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BaseCache::regStats()
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{
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using namespace Stats;
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// Hit statistics
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2007-02-07 19:53:37 +01:00
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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2006-06-28 17:02:14 +02:00
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hits[access_idx]
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.init(maxThreadsPerCPU)
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.name(name() + "." + cstr + "_hits")
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.desc("number of " + cstr + " hits")
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.flags(total | nozero | nonan)
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;
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}
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2007-06-30 22:34:16 +02:00
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// These macros make it easier to sum the right subset of commands and
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// to change the subset of commands that are considered "demand" vs
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// "non-demand"
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#define SUM_DEMAND(s) \
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(s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq])
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// should writebacks be included here? prior code was inconsistent...
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#define SUM_NON_DEMAND(s) \
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(s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
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2006-06-28 17:02:14 +02:00
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demandHits
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.name(name() + ".demand_hits")
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.desc("number of demand (read+write) hits")
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.flags(total)
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;
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2007-06-30 22:34:16 +02:00
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demandHits = SUM_DEMAND(hits);
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2006-06-28 17:02:14 +02:00
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overallHits
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.name(name() + ".overall_hits")
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.desc("number of overall hits")
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.flags(total)
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;
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2007-06-30 22:34:16 +02:00
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overallHits = demandHits + SUM_NON_DEMAND(hits);
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2006-06-28 17:02:14 +02:00
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// Miss statistics
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2007-02-07 19:53:37 +01:00
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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2006-06-28 17:02:14 +02:00
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misses[access_idx]
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.init(maxThreadsPerCPU)
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.name(name() + "." + cstr + "_misses")
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.desc("number of " + cstr + " misses")
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.flags(total | nozero | nonan)
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;
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}
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demandMisses
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.name(name() + ".demand_misses")
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.desc("number of demand (read+write) misses")
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.flags(total)
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;
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2007-06-30 22:34:16 +02:00
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demandMisses = SUM_DEMAND(misses);
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2006-06-28 17:02:14 +02:00
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overallMisses
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.name(name() + ".overall_misses")
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.desc("number of overall misses")
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.flags(total)
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;
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2007-06-30 22:34:16 +02:00
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overallMisses = demandMisses + SUM_NON_DEMAND(misses);
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2006-06-28 17:02:14 +02:00
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// Miss latency statistics
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2007-02-07 19:53:37 +01:00
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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2006-06-28 17:02:14 +02:00
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missLatency[access_idx]
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.init(maxThreadsPerCPU)
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.name(name() + "." + cstr + "_miss_latency")
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.desc("number of " + cstr + " miss cycles")
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.flags(total | nozero | nonan)
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;
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}
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demandMissLatency
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.name(name() + ".demand_miss_latency")
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.desc("number of demand (read+write) miss cycles")
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.flags(total)
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;
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2007-06-30 22:34:16 +02:00
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demandMissLatency = SUM_DEMAND(missLatency);
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2006-06-28 17:02:14 +02:00
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overallMissLatency
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.name(name() + ".overall_miss_latency")
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.desc("number of overall miss cycles")
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.flags(total)
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;
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2007-06-30 22:34:16 +02:00
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overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency);
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2006-06-28 17:02:14 +02:00
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// access formulas
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2007-02-07 19:53:37 +01:00
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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2006-06-28 17:02:14 +02:00
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accesses[access_idx]
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.name(name() + "." + cstr + "_accesses")
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.desc("number of " + cstr + " accesses(hits+misses)")
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.flags(total | nozero | nonan)
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;
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accesses[access_idx] = hits[access_idx] + misses[access_idx];
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}
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demandAccesses
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.name(name() + ".demand_accesses")
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.desc("number of demand (read+write) accesses")
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.flags(total)
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;
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demandAccesses = demandHits + demandMisses;
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overallAccesses
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.name(name() + ".overall_accesses")
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.desc("number of overall (read+write) accesses")
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.flags(total)
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;
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overallAccesses = overallHits + overallMisses;
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// miss rate formulas
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2007-02-07 19:53:37 +01:00
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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2006-06-28 17:02:14 +02:00
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missRate[access_idx]
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.name(name() + "." + cstr + "_miss_rate")
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.desc("miss rate for " + cstr + " accesses")
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.flags(total | nozero | nonan)
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;
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missRate[access_idx] = misses[access_idx] / accesses[access_idx];
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}
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demandMissRate
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.name(name() + ".demand_miss_rate")
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.desc("miss rate for demand accesses")
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.flags(total)
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;
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demandMissRate = demandMisses / demandAccesses;
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overallMissRate
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.name(name() + ".overall_miss_rate")
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.desc("miss rate for overall accesses")
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.flags(total)
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;
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overallMissRate = overallMisses / overallAccesses;
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// miss latency formulas
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2007-02-07 19:53:37 +01:00
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for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
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MemCmd cmd(access_idx);
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const string &cstr = cmd.toString();
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2006-06-28 17:02:14 +02:00
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avgMissLatency[access_idx]
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.name(name() + "." + cstr + "_avg_miss_latency")
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.desc("average " + cstr + " miss latency")
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.flags(total | nozero | nonan)
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;
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avgMissLatency[access_idx] =
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missLatency[access_idx] / misses[access_idx];
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}
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demandAvgMissLatency
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.name(name() + ".demand_avg_miss_latency")
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.desc("average overall miss latency")
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.flags(total)
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;
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demandAvgMissLatency = demandMissLatency / demandMisses;
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overallAvgMissLatency
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.name(name() + ".overall_avg_miss_latency")
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.desc("average overall miss latency")
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.flags(total)
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;
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overallAvgMissLatency = overallMissLatency / overallMisses;
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blocked_cycles.init(NUM_BLOCKED_CAUSES);
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blocked_cycles
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.name(name() + ".blocked_cycles")
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.desc("number of cycles access was blocked")
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.subname(Blocked_NoMSHRs, "no_mshrs")
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.subname(Blocked_NoTargets, "no_targets")
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;
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blocked_causes.init(NUM_BLOCKED_CAUSES);
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blocked_causes
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.name(name() + ".blocked")
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.desc("number of cycles access was blocked")
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.subname(Blocked_NoMSHRs, "no_mshrs")
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.subname(Blocked_NoTargets, "no_targets")
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;
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avg_blocked
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|
|
.name(name() + ".avg_blocked_cycles")
|
|
|
|
.desc("average number of cycles each access was blocked")
|
|
|
|
.subname(Blocked_NoMSHRs, "no_mshrs")
|
|
|
|
.subname(Blocked_NoTargets, "no_targets")
|
|
|
|
;
|
|
|
|
|
|
|
|
avg_blocked = blocked_cycles / blocked_causes;
|
|
|
|
|
|
|
|
fastWrites
|
|
|
|
.name(name() + ".fast_writes")
|
|
|
|
.desc("number of fast writes performed")
|
|
|
|
;
|
|
|
|
|
|
|
|
cacheCopies
|
|
|
|
.name(name() + ".cache_copies")
|
|
|
|
.desc("number of cache copies performed")
|
|
|
|
;
|
2006-06-30 22:25:35 +02:00
|
|
|
|
2007-06-18 02:27:53 +02:00
|
|
|
writebacks
|
|
|
|
.init(maxThreadsPerCPU)
|
|
|
|
.name(name() + ".writebacks")
|
|
|
|
.desc("number of writebacks")
|
|
|
|
.flags(total)
|
|
|
|
;
|
|
|
|
|
|
|
|
// MSHR statistics
|
|
|
|
// MSHR hit statistics
|
|
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
|
|
MemCmd cmd(access_idx);
|
|
|
|
const string &cstr = cmd.toString();
|
|
|
|
|
|
|
|
mshr_hits[access_idx]
|
|
|
|
.init(maxThreadsPerCPU)
|
|
|
|
.name(name() + "." + cstr + "_mshr_hits")
|
|
|
|
.desc("number of " + cstr + " MSHR hits")
|
|
|
|
.flags(total | nozero | nonan)
|
|
|
|
;
|
|
|
|
}
|
|
|
|
|
|
|
|
demandMshrHits
|
|
|
|
.name(name() + ".demand_mshr_hits")
|
|
|
|
.desc("number of demand (read+write) MSHR hits")
|
|
|
|
.flags(total)
|
|
|
|
;
|
2007-06-30 22:34:16 +02:00
|
|
|
demandMshrHits = SUM_DEMAND(mshr_hits);
|
2007-06-18 02:27:53 +02:00
|
|
|
|
|
|
|
overallMshrHits
|
|
|
|
.name(name() + ".overall_mshr_hits")
|
|
|
|
.desc("number of overall MSHR hits")
|
|
|
|
.flags(total)
|
|
|
|
;
|
2007-06-30 22:34:16 +02:00
|
|
|
overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits);
|
2007-06-18 02:27:53 +02:00
|
|
|
|
|
|
|
// MSHR miss statistics
|
|
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
|
|
MemCmd cmd(access_idx);
|
|
|
|
const string &cstr = cmd.toString();
|
|
|
|
|
|
|
|
mshr_misses[access_idx]
|
|
|
|
.init(maxThreadsPerCPU)
|
|
|
|
.name(name() + "." + cstr + "_mshr_misses")
|
|
|
|
.desc("number of " + cstr + " MSHR misses")
|
|
|
|
.flags(total | nozero | nonan)
|
|
|
|
;
|
|
|
|
}
|
|
|
|
|
|
|
|
demandMshrMisses
|
|
|
|
.name(name() + ".demand_mshr_misses")
|
|
|
|
.desc("number of demand (read+write) MSHR misses")
|
|
|
|
.flags(total)
|
|
|
|
;
|
2007-06-30 22:34:16 +02:00
|
|
|
demandMshrMisses = SUM_DEMAND(mshr_misses);
|
2007-06-18 02:27:53 +02:00
|
|
|
|
|
|
|
overallMshrMisses
|
|
|
|
.name(name() + ".overall_mshr_misses")
|
|
|
|
.desc("number of overall MSHR misses")
|
|
|
|
.flags(total)
|
|
|
|
;
|
2007-06-30 22:34:16 +02:00
|
|
|
overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses);
|
2007-06-18 02:27:53 +02:00
|
|
|
|
|
|
|
// MSHR miss latency statistics
|
|
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
|
|
MemCmd cmd(access_idx);
|
|
|
|
const string &cstr = cmd.toString();
|
|
|
|
|
|
|
|
mshr_miss_latency[access_idx]
|
|
|
|
.init(maxThreadsPerCPU)
|
|
|
|
.name(name() + "." + cstr + "_mshr_miss_latency")
|
|
|
|
.desc("number of " + cstr + " MSHR miss cycles")
|
|
|
|
.flags(total | nozero | nonan)
|
|
|
|
;
|
|
|
|
}
|
|
|
|
|
|
|
|
demandMshrMissLatency
|
|
|
|
.name(name() + ".demand_mshr_miss_latency")
|
|
|
|
.desc("number of demand (read+write) MSHR miss cycles")
|
|
|
|
.flags(total)
|
|
|
|
;
|
2007-06-30 22:34:16 +02:00
|
|
|
demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency);
|
2007-06-18 02:27:53 +02:00
|
|
|
|
|
|
|
overallMshrMissLatency
|
|
|
|
.name(name() + ".overall_mshr_miss_latency")
|
|
|
|
.desc("number of overall MSHR miss cycles")
|
|
|
|
.flags(total)
|
|
|
|
;
|
2007-06-30 22:34:16 +02:00
|
|
|
overallMshrMissLatency =
|
|
|
|
demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency);
|
2007-06-18 02:27:53 +02:00
|
|
|
|
|
|
|
// MSHR uncacheable statistics
|
|
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
|
|
MemCmd cmd(access_idx);
|
|
|
|
const string &cstr = cmd.toString();
|
|
|
|
|
|
|
|
mshr_uncacheable[access_idx]
|
|
|
|
.init(maxThreadsPerCPU)
|
|
|
|
.name(name() + "." + cstr + "_mshr_uncacheable")
|
|
|
|
.desc("number of " + cstr + " MSHR uncacheable")
|
|
|
|
.flags(total | nozero | nonan)
|
|
|
|
;
|
|
|
|
}
|
|
|
|
|
|
|
|
overallMshrUncacheable
|
|
|
|
.name(name() + ".overall_mshr_uncacheable_misses")
|
|
|
|
.desc("number of overall MSHR uncacheable misses")
|
|
|
|
.flags(total)
|
|
|
|
;
|
2007-06-30 22:34:16 +02:00
|
|
|
overallMshrUncacheable =
|
|
|
|
SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable);
|
2007-06-18 02:27:53 +02:00
|
|
|
|
|
|
|
// MSHR miss latency statistics
|
|
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
|
|
MemCmd cmd(access_idx);
|
|
|
|
const string &cstr = cmd.toString();
|
|
|
|
|
|
|
|
mshr_uncacheable_lat[access_idx]
|
|
|
|
.init(maxThreadsPerCPU)
|
|
|
|
.name(name() + "." + cstr + "_mshr_uncacheable_latency")
|
|
|
|
.desc("number of " + cstr + " MSHR uncacheable cycles")
|
|
|
|
.flags(total | nozero | nonan)
|
|
|
|
;
|
|
|
|
}
|
|
|
|
|
|
|
|
overallMshrUncacheableLatency
|
|
|
|
.name(name() + ".overall_mshr_uncacheable_latency")
|
|
|
|
.desc("number of overall MSHR uncacheable cycles")
|
|
|
|
.flags(total)
|
|
|
|
;
|
2007-06-30 22:34:16 +02:00
|
|
|
overallMshrUncacheableLatency =
|
|
|
|
SUM_DEMAND(mshr_uncacheable_lat) +
|
|
|
|
SUM_NON_DEMAND(mshr_uncacheable_lat);
|
2007-06-18 02:27:53 +02:00
|
|
|
|
|
|
|
#if 0
|
|
|
|
// MSHR access formulas
|
|
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
|
|
MemCmd cmd(access_idx);
|
|
|
|
const string &cstr = cmd.toString();
|
|
|
|
|
|
|
|
mshrAccesses[access_idx]
|
|
|
|
.name(name() + "." + cstr + "_mshr_accesses")
|
|
|
|
.desc("number of " + cstr + " mshr accesses(hits+misses)")
|
|
|
|
.flags(total | nozero | nonan)
|
|
|
|
;
|
|
|
|
mshrAccesses[access_idx] =
|
|
|
|
mshr_hits[access_idx] + mshr_misses[access_idx]
|
|
|
|
+ mshr_uncacheable[access_idx];
|
|
|
|
}
|
|
|
|
|
|
|
|
demandMshrAccesses
|
|
|
|
.name(name() + ".demand_mshr_accesses")
|
|
|
|
.desc("number of demand (read+write) mshr accesses")
|
|
|
|
.flags(total | nozero | nonan)
|
|
|
|
;
|
|
|
|
demandMshrAccesses = demandMshrHits + demandMshrMisses;
|
|
|
|
|
|
|
|
overallMshrAccesses
|
|
|
|
.name(name() + ".overall_mshr_accesses")
|
|
|
|
.desc("number of overall (read+write) mshr accesses")
|
|
|
|
.flags(total | nozero | nonan)
|
|
|
|
;
|
|
|
|
overallMshrAccesses = overallMshrHits + overallMshrMisses
|
|
|
|
+ overallMshrUncacheable;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
// MSHR miss rate formulas
|
|
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
|
|
MemCmd cmd(access_idx);
|
|
|
|
const string &cstr = cmd.toString();
|
|
|
|
|
|
|
|
mshrMissRate[access_idx]
|
|
|
|
.name(name() + "." + cstr + "_mshr_miss_rate")
|
|
|
|
.desc("mshr miss rate for " + cstr + " accesses")
|
|
|
|
.flags(total | nozero | nonan)
|
|
|
|
;
|
|
|
|
|
|
|
|
mshrMissRate[access_idx] =
|
|
|
|
mshr_misses[access_idx] / accesses[access_idx];
|
|
|
|
}
|
|
|
|
|
|
|
|
demandMshrMissRate
|
|
|
|
.name(name() + ".demand_mshr_miss_rate")
|
|
|
|
.desc("mshr miss rate for demand accesses")
|
|
|
|
.flags(total)
|
|
|
|
;
|
|
|
|
demandMshrMissRate = demandMshrMisses / demandAccesses;
|
|
|
|
|
|
|
|
overallMshrMissRate
|
|
|
|
.name(name() + ".overall_mshr_miss_rate")
|
|
|
|
.desc("mshr miss rate for overall accesses")
|
|
|
|
.flags(total)
|
|
|
|
;
|
|
|
|
overallMshrMissRate = overallMshrMisses / overallAccesses;
|
|
|
|
|
|
|
|
// mshrMiss latency formulas
|
|
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
|
|
MemCmd cmd(access_idx);
|
|
|
|
const string &cstr = cmd.toString();
|
|
|
|
|
|
|
|
avgMshrMissLatency[access_idx]
|
|
|
|
.name(name() + "." + cstr + "_avg_mshr_miss_latency")
|
|
|
|
.desc("average " + cstr + " mshr miss latency")
|
|
|
|
.flags(total | nozero | nonan)
|
|
|
|
;
|
|
|
|
|
|
|
|
avgMshrMissLatency[access_idx] =
|
|
|
|
mshr_miss_latency[access_idx] / mshr_misses[access_idx];
|
|
|
|
}
|
|
|
|
|
|
|
|
demandAvgMshrMissLatency
|
|
|
|
.name(name() + ".demand_avg_mshr_miss_latency")
|
|
|
|
.desc("average overall mshr miss latency")
|
|
|
|
.flags(total)
|
|
|
|
;
|
|
|
|
demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses;
|
|
|
|
|
|
|
|
overallAvgMshrMissLatency
|
|
|
|
.name(name() + ".overall_avg_mshr_miss_latency")
|
|
|
|
.desc("average overall mshr miss latency")
|
|
|
|
.flags(total)
|
|
|
|
;
|
|
|
|
overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
|
|
|
|
|
|
|
|
// mshrUncacheable latency formulas
|
|
|
|
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
|
|
|
|
MemCmd cmd(access_idx);
|
|
|
|
const string &cstr = cmd.toString();
|
|
|
|
|
|
|
|
avgMshrUncacheableLatency[access_idx]
|
|
|
|
.name(name() + "." + cstr + "_avg_mshr_uncacheable_latency")
|
|
|
|
.desc("average " + cstr + " mshr uncacheable latency")
|
|
|
|
.flags(total | nozero | nonan)
|
|
|
|
;
|
|
|
|
|
|
|
|
avgMshrUncacheableLatency[access_idx] =
|
|
|
|
mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx];
|
|
|
|
}
|
|
|
|
|
|
|
|
overallAvgMshrUncacheableLatency
|
|
|
|
.name(name() + ".overall_avg_mshr_uncacheable_latency")
|
|
|
|
.desc("average overall mshr uncacheable latency")
|
|
|
|
.flags(total)
|
|
|
|
;
|
|
|
|
overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable;
|
|
|
|
|
|
|
|
mshr_cap_events
|
|
|
|
.init(maxThreadsPerCPU)
|
|
|
|
.name(name() + ".mshr_cap_events")
|
|
|
|
.desc("number of times MSHR cap was activated")
|
|
|
|
.flags(total)
|
|
|
|
;
|
|
|
|
|
|
|
|
//software prefetching stats
|
|
|
|
soft_prefetch_mshr_full
|
|
|
|
.init(maxThreadsPerCPU)
|
|
|
|
.name(name() + ".soft_prefetch_mshr_full")
|
|
|
|
.desc("number of mshr full events for SW prefetching instrutions")
|
|
|
|
.flags(total)
|
|
|
|
;
|
|
|
|
|
|
|
|
mshr_no_allocate_misses
|
|
|
|
.name(name() +".no_allocate_misses")
|
|
|
|
.desc("Number of misses that were no-allocate")
|
|
|
|
;
|
|
|
|
|
2006-06-28 17:02:14 +02:00
|
|
|
}
|
2006-11-07 20:25:54 +01:00
|
|
|
|
|
|
|
unsigned int
|
|
|
|
BaseCache::drain(Event *de)
|
|
|
|
{
|
2007-06-18 02:27:53 +02:00
|
|
|
int count = memSidePort->drain(de) + cpuSidePort->drain(de);
|
|
|
|
|
2006-11-07 20:25:54 +01:00
|
|
|
// Set status
|
2007-06-18 02:27:53 +02:00
|
|
|
if (count != 0) {
|
2006-11-07 20:25:54 +01:00
|
|
|
drainEvent = de;
|
|
|
|
|
|
|
|
changeState(SimObject::Draining);
|
2007-06-18 02:27:53 +02:00
|
|
|
return count;
|
2006-11-07 20:25:54 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
changeState(SimObject::Drained);
|
|
|
|
return 0;
|
|
|
|
}
|