gem5/src/mem
Steve Reinhardt 4a7d0c4b79 bus: take out response prioritization (timing was messed up).
Also make express snoops not occupy bus (since they're magic).

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extra : convert_revision : 75aa5211a59380026d1e3f122778425e48e2edcd
2007-07-29 13:24:48 -07:00
..
cache cache/memtest: fixes for functional accesses. 2007-07-27 12:46:45 -07:00
config Backing in more changsets, getting closer to compile 2006-06-28 14:35:00 -04:00
bridge.cc Merge python and x86 changes with cache branch 2007-07-26 23:15:49 -07:00
bridge.hh Merge python and x86 changes with cache branch 2007-07-26 23:15:49 -07:00
Bridge.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
bus.cc bus: take out response prioritization (timing was messed up). 2007-07-29 13:24:48 -07:00
bus.hh Integrate snoop loop functions into their respective call sites. 2007-07-24 22:37:41 -07:00
Bus.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
dram.cc Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
dram.hh Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
mem_object.cc Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
mem_object.hh Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
MemObject.py Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
packet.cc packet: get rid of unused intersect() function. 2007-07-27 12:46:55 -07:00
packet.hh packet: get rid of unused intersect() function. 2007-07-27 12:46:55 -07:00
packet_access.hh Make byteswap work correctly on Twin??_t types. 2007-03-07 17:46:04 +00:00
page_table.cc Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
page_table.hh Clean up some of vincent's code and commit it 2007-06-05 01:03:35 -04:00
physical.cc Merge python and x86 changes with cache branch 2007-07-26 23:15:49 -07:00
physical.hh Merge python and x86 changes with cache branch 2007-07-26 23:15:49 -07:00
PhysicalMemory.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
port.cc Get rid of Packet result field. Error responses are 2007-06-30 10:16:18 -07:00
port.hh Change getDeviceAddressRanges to use bool for snoop arg. 2007-05-21 23:36:09 -07:00
port_impl.hh Put the ProcessInfo and StackTrace objects into the ISA namespaces. 2006-11-08 00:52:04 -05:00
request.hh Use FastAlloc for Packet, Request, CoherenceState, and SenderState so we don't spend so much time calling malloc() 2007-06-21 13:50:35 -04:00
SConscript Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
tport.cc Don't delete request at target... requester still needs it. 2007-07-24 22:36:10 -07:00
tport.hh Fix up a few statistics problems. 2007-06-30 13:34:16 -07:00
translating_port.cc fix the translating ports so it can add a page on a fault 2007-05-09 15:37:46 -04:00
translating_port.hh fix the translating ports so it can add a page on a fault 2007-05-09 15:37:46 -04:00
vport.cc implement vtophys and 32bit gdb support 2007-02-18 19:57:46 -05:00
vport.hh implement vtophys and 32bit gdb support 2007-02-18 19:57:46 -05:00