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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
sim_seconds 51.111151 # Number of seconds simulated
sim_ticks 51111150553500 # Number of ticks simulated
final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
host_inst_rate 1336104 # Simulator instruction rate (inst/s)
host_op_rate 1570142 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 69344550867 # Simulator tick rate (ticks/s)
host_mem_usage 712616 # Number of bytes of host memory used
host_seconds 737.06 # Real time elapsed on the host
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
sim_insts 984789519 # Number of instructions simulated
sim_ops 1157289961 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_read::cpu.dtb.walker 411136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 373504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 5556020 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 75320200 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory
system.physmem.bytes_read::total 82098556 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5556020 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5556020 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 103277568 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::total 103298148 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 6424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5836 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 127220 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1176891 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1323210 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1613712 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1616285 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 8044 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 7308 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 108705 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1473655 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8564 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1606275 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 108705 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 108705 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2020647 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2021049 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2020647 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 8044 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 7308 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 108705 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1474058 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8564 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3627324 # Total bandwidth to/from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walks 265618 # Table walker walks requested
system.cpu.dtb.walker.walksLong 265618 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walkWaitTime::samples 265618 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0 265618 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 265618 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 204344 89.54% 89.54% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 23878 10.46% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 228222 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265618 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265618 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228222 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228222 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 493840 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.read_hits 184057973 # DTB read hits
system.cpu.dtb.read_misses 194269 # DTB read misses
system.cpu.dtb.write_hits 168276300 # DTB write hits
system.cpu.dtb.write_misses 71349 # DTB write misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.flush_entries 81439 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.prefetch_faults 9105 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.read_accesses 184252242 # DTB read accesses
system.cpu.dtb.write_accesses 168347649 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.hits 352334273 # DTB hits
system.cpu.dtb.misses 265618 # DTB misses
system.cpu.dtb.accesses 352599891 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 126829 # Table walker walks requested
system.cpu.itb.walker.walksLong 126829 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walkWaitTime::samples 126829 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0 126829 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 126829 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 113566 99.02% 99.02% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M 1125 0.98% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 114691 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126829 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 126829 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114691 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 114691 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 241520 # Table walker requests started/completed, data/inst
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.itb.inst_hits 985266544 # ITB inst hits
system.cpu.itb.inst_misses 126829 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.itb.flush_entries 57079 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.itb.inst_accesses 985393373 # ITB inst accesses
system.cpu.itb.hits 985266544 # DTB hits
system.cpu.itb.misses 126829 # DTB misses
system.cpu.itb.accesses 985393373 # DTB accesses
system.cpu.numCycles 102222317883 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.committedInsts 984789519 # Number of instructions committed
system.cpu.committedOps 1157289961 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1060698532 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 880773 # Number of float alu accesses
system.cpu.num_func_calls 57075493 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 151966445 # number of instructions that are conditional controls
system.cpu.num_int_insts 1060698532 # number of integer instructions
system.cpu.num_fp_insts 880773 # number of float instructions
system.cpu.num_int_register_reads 1564314393 # number of times the integer registers were read
system.cpu.num_int_register_writes 842633326 # number of times the integer registers were written
system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read
system.cpu.num_fp_register_writes 747792 # number of times the floating registers were written
system.cpu.num_cc_register_reads 264443211 # number of times the CC registers were read
system.cpu.num_cc_register_writes 263865511 # number of times the CC registers were written
system.cpu.num_mem_refs 352552781 # number of memory refs
system.cpu.num_load_insts 184224242 # Number of load instructions
system.cpu.num_store_insts 168328539 # Number of store instructions
system.cpu.num_idle_cycles 101064381138.333679 # Number of idle cycles
system.cpu.num_busy_cycles 1157936744.666323 # Number of busy cycles
system.cpu.not_idle_fraction 0.011328 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.988672 # Percentage of idle cycles
system.cpu.Branches 220135160 # Number of branches fetched
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.op_class::IntAlu 802806903 69.33% 69.33% # Class of executed instruction
system.cpu.op_class::IntMult 2355402 0.20% 69.53% # Class of executed instruction
system.cpu.op_class::IntDiv 101851 0.01% 69.54% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 8 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 13 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 21 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::MemRead 184224242 15.91% 85.46% # Class of executed instruction
system.cpu.op_class::MemWrite 168328539 14.54% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.op_class::total 1157924802 # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.replacements 11615783 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.999718 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 340859576 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 11616295 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 29.343227 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999718 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1421519854 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1421519854 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 171606610 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 171606610 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 159566138 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 159566138 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 424146 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 424146 # number of SoftPFReq hits
system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337798 # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_hits::total 337798 # number of WriteInvalidateReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310377 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 4310377 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 4563246 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 4563246 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 331172748 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 331172748 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 331596894 # number of overall hits
system.cpu.dcache.overall_hits::total 331596894 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 6013361 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 6013361 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2569466 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2569466 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1584813 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1584813 # number of SoftPFReq misses
system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245259 # number of WriteInvalidateReq misses
system.cpu.dcache.WriteInvalidateReq_misses::total 1245259 # number of WriteInvalidateReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 254671 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 254671 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 8582827 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 8582827 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 10167640 # number of overall misses
system.cpu.dcache.overall_misses::total 10167640 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 177619971 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 177619971 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 162135604 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 162135604 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008959 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2008959 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583057 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::total 1583057 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4565048 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 4565048 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 4563247 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 4563247 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 339755575 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 339755575 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 341764534 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 341764534 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033855 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.033855 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015848 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015848 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788873 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.788873 # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786617 # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786617 # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055787 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055787 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.025262 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.025262 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.029750 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.029750 # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 8923646 # number of writebacks
system.cpu.dcache.writebacks::total 8923646 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 14287218 # number of replacements
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.tags.total_refs 971093500 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 14287730 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 67.966955 # Average number of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.tags.tag_accesses 999668970 # Number of tag accesses
system.cpu.icache.tags.data_accesses 999668970 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 971093500 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 971093500 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 971093500 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 971093500 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 971093500 # number of overall hits
system.cpu.icache.overall_hits::total 971093500 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 14287735 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 14287735 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 14287735 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 14287735 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 14287735 # number of overall misses
system.cpu.icache.overall_misses::total 14287735 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 985381235 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 985381235 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 985381235 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 985381235 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 985381235 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 985381235 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014500 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.014500 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.014500 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.014500 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.014500 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.014500 # miss rate for overall accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.replacements 1726949 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65261.456081 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 29978708 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1789688 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 16.750801 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 37844.065183 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 274.121350 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 368.710071 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6273.950851 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 20500.608627 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.577455 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004183 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005626 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095733 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.312814 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.995811 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 248 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 62491 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 241 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 597 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2750 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4968 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54019 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003784 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953537 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 290358067 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 290358067 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 511193 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 258912 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 14203603 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 7508372 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 22482080 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 8923646 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 8923646 # number of Writeback hits
system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 697316 # number of WriteInvalidateReq hits
system.cpu.l2cache.WriteInvalidateReq_hits::total 697316 # number of WriteInvalidateReq hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 11232 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 11232 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1684603 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1684603 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 511193 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 258912 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 14203603 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 9192975 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 24166683 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 511193 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 258912 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 14203603 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 9192975 # number of overall hits
system.cpu.l2cache.overall_hits::total 24166683 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6424 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5836 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 84132 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 344473 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 440865 # number of ReadReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 547943 # number of WriteInvalidateReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::total 547943 # number of WriteInvalidateReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 40028 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 40028 # number of UpgradeReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 833603 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 833603 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 6424 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 5836 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 84132 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1178076 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1274468 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 6424 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 5836 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 84132 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1178076 # number of overall misses
system.cpu.l2cache.overall_misses::total 1274468 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 517617 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 264748 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 14287735 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7852845 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 22922945 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 8923646 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 8923646 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1245259 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::total 1245259 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51260 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 51260 # number of UpgradeReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2518206 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2518206 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 517617 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 264748 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 14287735 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 10371051 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 25441151 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 517617 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 264748 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 14287735 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 10371051 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 25441151 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012411 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022044 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005888 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043866 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.019232 # miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.440023 # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.440023 # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780882 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780882 # miss rate for UpgradeReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.331031 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.331031 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012411 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022044 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005888 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.113593 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.050095 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012411 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022044 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005888 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.113593 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.050095 # miss rate for overall accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.writebacks::writebacks 1507081 # number of writebacks
system.cpu.l2cache.writebacks::total 1507081 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 23368238 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 23368238 # Transaction distribution
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.trans_dist::WriteReq 33712 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33712 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.trans_dist::Writeback 8923646 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245259 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245259 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 51260 # Transaction distribution
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.trans_dist::UpgradeResp 51261 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2518206 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2518206 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28661720 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32393426 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758172 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543680 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 63356998 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 914587540 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314747172 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6174720 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2238542120 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 116335 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 36145396 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 5.003196 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.056442 # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::5 36029878 99.68% 99.68% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 115518 0.32% 100.00% # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::total 36145396 # Request fanout histogram
system.iobus.trans_dist::ReadReq 40296 # Transaction distribution
system.iobus.trans_dist::ReadResp 40296 # Transaction distribution
system.iobus.trans_dist::WriteReq 136621 # Transaction distribution
system.iobus.trans_dist::WriteResp 29957 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7492270 # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.replacements 115460 # number of replacements
system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.tags.sampled_refs 115476 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.tags.occ_blocks::realview.ethernet 3.554601 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.852508 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.222163 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.tags.tag_accesses 1039659 # Number of tag accesses
system.iocache.tags.data_accesses 1039659 # Number of data accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses
system.iocache.demand_misses::total 8854 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_misses::realview.ide 8814 # number of overall misses
system.iocache.overall_misses::total 8854 # number of overall misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.trans_dist::ReadReq 526448 # Transaction distribution
system.membus.trans_dist::ReadResp 526448 # Transaction distribution
system.membus.trans_dist::WriteReq 33712 # Transaction distribution
system.membus.trans_dist::WriteResp 33712 # Transaction distribution
system.membus.trans_dist::Writeback 1613712 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 654602 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 654602 # Transaction distribution
system.membus.trans_dist::UpgradeReq 40596 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
system.membus.trans_dist::UpgradeResp 40597 # Transaction distribution
system.membus.trans_dist::ReadExReq 833043 # Transaction distribution
system.membus.trans_dist::ReadExResp 833043 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5323339 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5452849 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337667 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 337667 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5790516 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 213244448 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 213413816 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217344 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 14217344 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 227631160 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 3591670 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 3591670 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 3591670 # Request fanout histogram
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
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