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gem5/tests/configs/tgen-simple-mem.py

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TrafficGen: Add a basic traffic generator regression This patch adds a basic regression for the traffic generator. The regression also serves as an example of the file formats used. More complex regressions that make use of a DRAM controller model will follow shortly.
2012-09-21 17:48:11 +02:00
# Copyright (c) 2012 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Hansson
import m5
from m5.objects import *
cpu: Add support for protobuf input for the trace generator This patch adds support for reading input traces encoded using protobuf according to what is done in the CommMonitor. A follow-up patch adds a Python script that can be used to convert the previously used ASCII traces to protobuf equivalents. The appropriate regression input is updated as part of this patch.
2013-01-07 19:05:37 +01:00
# both traffic generator and communication monitor are only available
# if we have protobuf support, so potentially skip this test
require_sim_object("TrafficGen")
require_sim_object("CommMonitor")
TrafficGen: Add a basic traffic generator regression This patch adds a basic regression for the traffic generator. The regression also serves as an example of the file formats used. More complex regressions that make use of a DRAM controller model will follow shortly.
2012-09-21 17:48:11 +02:00
# even if this is only a traffic generator, call it cpu to make sure
# the scripts are happy
tests: Remove working dir assumption in tgen tests The traffic generator tests currently assume that they are run from the root of the source directory. This sometimes breaks tests when they are run using the new test framework. Change-Id: I6538a7902694c5d2c980295e076ea1c09acc4291 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-06-02 16:20:24 +02:00
cpu = TrafficGen(
config_file=srcpath("tests/quick/se/70.tgen/tgen-simple-mem.cfg"))
TrafficGen: Add a basic traffic generator regression This patch adds a basic regression for the traffic generator. The regression also serves as an example of the file formats used. More complex regressions that make use of a DRAM controller model will follow shortly.
2012-09-21 17:48:11 +02:00
# system simulated
system = System(cpu = cpu, physmem = SimpleMemory(),
mem: Move crossbar default latencies to subclasses This patch introduces a few subclasses to the CoherentXBar and NoncoherentXBar to distinguish the different uses in the system. We use the crossbar in a wide range of places: interfacing cores to the L2, as a system interconnect, connecting I/O and peripherals, etc. Needless to say, these crossbars have very different performance, and the clock frequency alone is not enough to distinguish these scenarios. Instead of trying to capture every possible case, this patch introduces dedicated subclasses for the three primary use-cases: L2XBar, SystemXBar and IOXbar. More can be added if needed, and the defaults can be overridden.
2015-03-02 10:00:47 +01:00
membus = IOXBar(width = 16),
power: Add voltage domains to the clock domains This patch adds the notion of voltage domains, and groups clock domains that operate under the same voltage (i.e. power supply) into domains. Each clock domain is required to be associated with a voltage domain, and the latter requires the voltage to be explicitly set. A voltage domain is an independently controllable voltage supply being provided to section of the design. Thus, if you wish to perform dynamic voltage scaling on a CPU, its clock domain should be associated with a separate voltage domain. The current implementation of the voltage domain does not take into consideration cases where there are derived voltage domains running at ratio of native voltage domains, as with the case where there can be on-chip buck/boost (charge pumps) voltage regulation logic. The regression and configuration scripts are updated with a generic voltage domain for the system, and one for the CPUs.
2013-08-19 09:52:28 +02:00
clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain =
VoltageDomain()))
TrafficGen: Add a basic traffic generator regression This patch adds a basic regression for the traffic generator. The regression also serves as an example of the file formats used. More complex regressions that make use of a DRAM controller model will follow shortly.
2012-09-21 17:48:11 +02:00
tests: Add a regression for the stack distance calculator Re-use the existing traffic generator regression, and enable the stack distance calculation in the comm monitor, along with the verification stack. The traffic generator config is also tuned to not increase the run-time too much (and actually have some address re-use).
2014-12-23 15:31:18 +01:00
# add a communication monitor, and also trace all the packets and
# calculate and verify stack distance
mem: Move trace functionality from the CommMonitor to a probe This changeset moves the access trace functionality from the CommMonitor into a separate probe. The probe can be hooked up to any component that exports probe points of the type ProbePoints::Packet. This patch moves the dependency on Google's Protocol Buffers library from the CommMonitor to the MemTraceProbe, which means that the CommMonitor (including stack distance profiling) no long depends on it.
2015-08-04 11:29:13 +02:00
system.monitor = CommMonitor()
system.monitor.trace = MemTraceProbe(trace_file = "monitor.ptrc.gz")
mem: Redesign the stack distance calculator as a probe This changeset removes the stack distance calculator hooks from the CommMonitor class and implements a stack distance calculator as a memory system probe instead. The probe can be hooked up to any component that exports probe points of the type ProbePoints::Packet.
2015-08-04 11:29:13 +02:00
system.monitor.stackdist = StackDistProbe(verify = True)
TrafficGen: Add a basic traffic generator regression This patch adds a basic regression for the traffic generator. The regression also serves as an example of the file formats used. More complex regressions that make use of a DRAM controller model will follow shortly.
2012-09-21 17:48:11 +02:00
# connect the traffic generator to the bus via a communication monitor
system.cpu.port = system.monitor.slave
system.monitor.master = system.membus.slave
# connect the system port even if it is not used in this example
system.system_port = system.membus.slave
# connect memory to the membus
system.physmem.port = system.membus.master
# -----------------------
# run simulation
# -----------------------
root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'
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