c8919e6537
Last year, right before I sent xv6 to the printer, I changed the SETGATE calls so that interrupts would be disabled on entry to interrupt handlers, and I added the nlock++ / nlock-- in trap() so that interrupts would stay disabled while the hw handlers (but not the syscall handler) did their work. I did this because the kernel was otherwise causing Bochs to triple-fault in SMP mode, and time was short. Robert observed yesterday that something was keeping the SMP preemption user test from working. It turned out that when I simplified the lapic code I swapped the order of two register writes that I didn't realize were order dependent. I fixed that and then since I had everything paged in kept going and tried to figure out why you can't leave interrupts on during interrupt handlers. There are a few issues. First, there must be some way to keep interrupts from "stacking up" and overflowing the stack. Keeping interrupts off the whole time solves this problem -- even if the clock tick handler runs long enough that the next clock tick is waiting when it finishes, keeping interrupts off means that the handler runs all the way through the "iret" before the next handler begins. This is not really a problem unless you are putting too many prints in trap -- if the OS is doing its job right, the handlers should run quickly and not stack up. Second, if xv6 had page faults, then it would be important to keep interrupts disabled between the start of the interrupt and the time that cr2 was read, to avoid a scenario like: p1 page faults [cr2 set to faulting address] p1 starts executing trapasm.S clock interrupt, p1 preempted, p2 starts executing p2 page faults [cr2 set to another faulting address] p2 starts, finishes fault handler p1 rescheduled, reads cr2, sees wrong fault address Alternately p1 could be rescheduled on the other cpu, in which case it would still see the wrong cr2. That said, I think cr2 is the only interrupt state that isn't pushed onto the interrupt stack atomically at fault time, and xv6 doesn't care. (This isn't entirely hypothetical -- I debugged this problem on Plan 9.) Third, and this is the big one, it is not safe to call cpu() unless interrupts are disabled. If interrupts are enabled then there is no guarantee that, between the time cpu() looks up the cpu id and the time that it the result gets used, the process has not been rescheduled to the other cpu. For example, the very commonly-used expression curproc[cpu()] (aka the macro cp) can end up referring to the wrong proc: the code stores the result of cpu() in %eax, gets rescheduled to the other cpu at just the wrong instant, and then reads curproc[%eax]. We use curproc[cpu()] to get the current process a LOT. In that particular case, if we arranged for the current curproc entry to be addressed by %fs:0 and just use a different %fs on each CPU, then we could safely get at curproc even with interrupts disabled, since the read of %fs would be atomic with the read of %fs:0. Alternately, we could have a curproc() function that disables interrupts while computing curproc[cpu()]. I've done that last one. Even in the current kernel, with interrupts off on entry to trap, interrupts are enabled inside release if there are no locks held. Also, the scheduler's idle loop must be interruptible at times so that the clock and disk interrupts (which might make processes runnable) can be handled. In addition to the rampant use of curproc[cpu()], this little snippet from acquire is wrong on smp: if(cpus[cpu()].nlock == 0) cli(); cpus[cpu()].nlock++; because if interrupts are off then we might call cpu(), get rescheduled to a different cpu, look at cpus[oldcpu].nlock, and wrongly decide not to disable interrupts on the new cpu. The fix is to always call cli(). But this is wrong too: if(holding(lock)) panic("acquire"); cli(); cpus[cpu()].nlock++; because holding looks at cpu(). The fix is: cli(); if(holding(lock)) panic("acquire"); cpus[cpu()].nlock++; I've done that, and I changed cpu() to complain the first time it gets called with interrupts disabled. (It gets called too much to complain every time.) I added new functions splhi and spllo that are like acquire and release but without the locking: void splhi(void) { cli(); cpus[cpu()].nsplhi++; } void spllo(void) { if(--cpus[cpu()].nsplhi == 0) sti(); } and I've used those to protect other sections of code that refer to cpu() when interrupts would otherwise be disabled (basically just curproc and setupsegs). I also use them in acquire/release and got rid of nlock. I'm not thrilled with the names, but I think the concept -- a counted cli/sti -- is sound. Having them also replaces the nlock++/nlock-- in trap.c and main.c, which is nice. Final note: it's still not safe to enable interrupts in the middle of trap() between lapic_eoi and returning to user space. I don't understand why, but we get a fault on pop %es because 0x10 is a bad segment descriptor (!) and then the fault faults trying to go into a new interrupt because 0x8 is a bad segment descriptor too! Triple fault. I haven't debugged this yet.
154 lines
4.4 KiB
C
154 lines
4.4 KiB
C
// The local APIC manages internal (non-I/O) interrupts.
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// See Chapter 8 & Appendix C of Intel processor manual volume 3.
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#include "types.h"
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#include "defs.h"
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#include "traps.h"
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#include "mmu.h"
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#include "x86.h"
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// Local APIC registers, divided by 4 for use as uint[] indices.
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#define ID (0x0020/4) // ID
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#define VER (0x0030/4) // Version
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#define TPR (0x0080/4) // Task Priority
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#define EOI (0x00B0/4) // EOI
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#define SVR (0x00F0/4) // Spurious Interrupt Vector
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#define ENABLE 0x00000100 // Unit Enable
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#define ESR (0x0280/4) // Error Status
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#define ICRLO (0x0300/4) // Interrupt Command
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#define INIT 0x00000500 // INIT/RESET
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#define STARTUP 0x00000600 // Startup IPI
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#define DELIVS 0x00001000 // Delivery status
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#define ASSERT 0x00004000 // Assert interrupt (vs deassert)
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#define LEVEL 0x00008000 // Level triggered
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#define BCAST 0x00080000 // Send to all APICs, including self.
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#define ICRHI (0x0310/4) // Interrupt Command [63:32]
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#define TIMER (0x0320/4) // Local Vector Table 0 (TIMER)
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#define X1 0x0000000B // divide counts by 1
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#define PERIODIC 0x00020000 // Periodic
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#define PCINT (0x0340/4) // Performance Counter LVT
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#define LINT0 (0x0350/4) // Local Vector Table 1 (LINT0)
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#define LINT1 (0x0360/4) // Local Vector Table 2 (LINT1)
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#define ERROR (0x0370/4) // Local Vector Table 3 (ERROR)
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#define MASKED 0x00010000 // Interrupt masked
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#define TICR (0x0380/4) // Timer Initial Count
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#define TCCR (0x0390/4) // Timer Current Count
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#define TDCR (0x03E0/4) // Timer Divide Configuration
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volatile uint *lapic; // Initialized in mp.c
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//PAGEBREAK!
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void
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lapic_init(int c)
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{
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if(!lapic)
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return;
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// Enable local APIC; set spurious interrupt vector.
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lapic[SVR] = ENABLE | (IRQ_OFFSET+IRQ_SPURIOUS);
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// The timer repeatedly counts down at bus frequency
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// from lapic[TICR] and then issues an interrupt.
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// If xv6 cared more about precise timekeeping,
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// TICR would be calibrated using an external time source.
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lapic[TDCR] = X1;
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lapic[TIMER] = PERIODIC | (IRQ_OFFSET + IRQ_TIMER);
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lapic[TICR] = 10000000;
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// Disable logical interrupt lines.
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lapic[LINT0] = MASKED;
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lapic[LINT1] = MASKED;
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// Disable performance counter overflow interrupts
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// on machines that provide that interrupt entry.
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if(((lapic[VER]>>16) & 0xFF) >= 4)
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lapic[PCINT] = MASKED;
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// Map error interrupt to IRQ_ERROR.
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lapic[ERROR] = IRQ_OFFSET+IRQ_ERROR;
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// Clear error status register (requires back-to-back writes).
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lapic[ESR] = 0;
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lapic[ESR] = 0;
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// Ack any outstanding interrupts.
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lapic[EOI] = 0;
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// Send an Init Level De-Assert to synchronise arbitration ID's.
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lapic[ICRHI] = 0;
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lapic[ICRLO] = BCAST | INIT | LEVEL;
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while(lapic[ICRLO] & DELIVS)
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;
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// Enable interrupts on the APIC (but not on the processor).
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lapic[TPR] = 0;
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}
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int
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cpu(void)
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{
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// Cannot call cpu when interrupts are enabled:
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// result not guaranteed to last long enough to be used!
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// Would prefer to panic but even printing is chancy here:
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// everything, including cprintf, calls cpu, at least indirectly
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// through acquire and release.
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if(read_eflags()&FL_IF){
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static int n;
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int i;
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uint pcs[10];
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if(n++%999 == 0){
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getcallerpcs((uint*)read_ebp() + 2, pcs);
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cprintf("cpu called from %x with interrupts enabled: stk");
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for(i=0; i<10 && pcs[i] && pcs[i] != -1; i++)
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cprintf(" %x", pcs[i]);
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cprintf("\n");
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}
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}
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if(lapic)
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return lapic[ID]>>24;
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return 0;
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}
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// Acknowledge interrupt.
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void
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lapic_eoi(void)
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{
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if(lapic)
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lapic[EOI] = 0;
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}
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// Spin for a given number of microseconds.
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// On real hardware would want to tune this dynamically.
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static void
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microdelay(int us)
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{
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volatile int j = 0;
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while(us-- > 0)
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for(j=0; j<10000; j++);
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}
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// Start additional processor running bootstrap code at addr.
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// See Appendix B of MultiProcessor Specification.
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void
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lapic_startap(uchar apicid, uint addr)
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{
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int i;
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volatile int j = 0;
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// Send INIT interrupt to reset other CPU.
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lapic[ICRHI] = apicid<<24;
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lapic[ICRLO] = INIT | LEVEL;
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microdelay(10);
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// Send startup IPI (twice!) to enter bootstrap code.
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// Regular hardware wants it twice, but Bochs complains.
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// Too bad for Bochs.
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for(i = 0; i < 2; i++){
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lapic[ICRHI] = apicid<<24;
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lapic[ICRLO] = STARTUP | (addr>>12);
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for(j=0; j<10000; j++); // 200us
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}
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}
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