134 lines
3.8 KiB
C
134 lines
3.8 KiB
C
// The local APIC manages internal (non-I/O) interrupts.
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// See Chapter 8 & Appendix C of Intel processor manual volume 3.
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#include "types.h"
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#include "traps.h"
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// Local APIC registers, divided by 4 for use as uint[] indices.
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#define ID (0x0020/4) // ID
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#define VER (0x0030/4) // Version
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#define TPR (0x0080/4) // Task Priority
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#define EOI (0x00B0/4) // EOI
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#define SVR (0x00F0/4) // Spurious Interrupt Vector
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#define ENABLE 0x00000100 // Unit Enable
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#define ESR (0x0280/4) // Error Status
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#define ICRLO (0x0300/4) // Interrupt Command
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#define INIT 0x00000500 // INIT/RESET
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#define STARTUP 0x00000600 // Startup IPI
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#define DELIVS 0x00001000 // Delivery status
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#define ASSERT 0x00004000 // Assert interrupt (vs deassert)
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#define LEVEL 0x00008000 // Level triggered
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#define BCAST 0x00080000 // Send to all APICs, including self.
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#define ICRHI (0x0310/4) // Interrupt Command [63:32]
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#define TIMER (0x0320/4) // Local Vector Table 0 (TIMER)
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#define X1 0x0000000B // divide counts by 1
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#define PERIODIC 0x00020000 // Periodic
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#define PCINT (0x0340/4) // Performance Counter LVT
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#define LINT0 (0x0350/4) // Local Vector Table 1 (LINT0)
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#define LINT1 (0x0360/4) // Local Vector Table 2 (LINT1)
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#define ERROR (0x0370/4) // Local Vector Table 3 (ERROR)
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#define MASKED 0x00010000 // Interrupt masked
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#define TICR (0x0380/4) // Timer Initial Count
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#define TCCR (0x0390/4) // Timer Current Count
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#define TDCR (0x03E0/4) // Timer Divide Configuration
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volatile uint *lapic; // Initialized in mp.c
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//PAGEBREAK!
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void
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lapic_init(int c)
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{
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if(!lapic)
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return;
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// Enable local APIC; set spurious interrupt vector.
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lapic[SVR] = ENABLE | (IRQ_OFFSET+IRQ_SPURIOUS);
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// The timer repeatedly counts down at bus frequency
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// from lapic[TICR] and then issues an interrupt.
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// Lapic[TCCR] is the current counter value.
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// If xv6 cared more about precise timekeeping, the
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// values of TICR and TCCR would be calibrated using
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// an external time source.
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lapic[TDCR] = X1;
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lapic[TICR] = 10000000;
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lapic[TCCR] = 10000000;
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lapic[TIMER] = PERIODIC | (IRQ_OFFSET + IRQ_TIMER);
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// Disable logical interrupt lines.
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lapic[LINT0] = MASKED;
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lapic[LINT1] = MASKED;
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// Disable performance counter overflow interrupts
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// on machines that provide that interrupt entry.
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if(((lapic[VER]>>16) & 0xFF) >= 4)
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lapic[PCINT] = MASKED;
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// Map error interrupt to IRQ_ERROR.
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lapic[ERROR] = IRQ_OFFSET+IRQ_ERROR;
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// Clear error status register (requires back-to-back writes).
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lapic[ESR] = 0;
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lapic[ESR] = 0;
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// Ack any outstanding interrupts.
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lapic[EOI] = 0;
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// Send an Init Level De-Assert to synchronise arbitration ID's.
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lapic[ICRHI] = 0;
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lapic[ICRLO] = BCAST | INIT | LEVEL;
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while(lapic[ICRLO] & DELIVS)
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;
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// Enable interrupts on the APIC (but not on the processor).
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lapic[TPR] = 0;
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}
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int
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cpu(void)
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{
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if(lapic)
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return lapic[ID]>>24;
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return 0;
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}
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// Acknowledge interrupt.
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void
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lapic_eoi(void)
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{
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if(lapic)
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lapic[EOI] = 0;
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}
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// Spin for a given number of microseconds.
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// On real hardware would want to tune this dynamically.
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static void
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microdelay(int us)
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{
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volatile int j = 0;
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while(us-- > 0)
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for(j=0; j<10000; j++);
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}
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// Start additional processor running bootstrap code at addr.
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// See Appendix B of MultiProcessor Specification.
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void
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lapic_startap(uchar apicid, uint addr)
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{
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int i;
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volatile int j = 0;
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// Send INIT interrupt to reset other CPU.
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lapic[ICRHI] = apicid<<24;
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lapic[ICRLO] = INIT | LEVEL;
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microdelay(10);
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// Send startup IPI (twice!) to enter bootstrap code.
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for(i = 0; i < 2; i++){
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lapic[ICRHI] = apicid<<24;
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lapic[ICRLO] = STARTUP | (addr>>12);
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for(j=0; j<10000; j++); // 200us
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}
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}
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