2de1c550ca
IRQ_OFFSET -> T_IRQ0 (a trap number not an IRQ number) T_SYSCALL 0x30 -> 0x40 (move out of IRQ range)
84 lines
2.3 KiB
C
84 lines
2.3 KiB
C
// Intel 8259A programmable interrupt controllers.
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#include "types.h"
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#include "x86.h"
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#include "traps.h"
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// I/O Addresses of the two programmable interrupt controllers
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#define IO_PIC1 0x20 // Master (IRQs 0-7)
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#define IO_PIC2 0xA0 // Slave (IRQs 8-15)
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#define IRQ_SLAVE 2 // IRQ at which slave connects to master
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// Current IRQ mask.
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// Initial IRQ mask has interrupt 2 enabled (for slave 8259A).
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static ushort irqmask = 0xFFFF & ~(1<<IRQ_SLAVE);
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static void
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picsetmask(ushort mask)
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{
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irqmask = mask;
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outb(IO_PIC1+1, mask);
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outb(IO_PIC2+1, mask >> 8);
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}
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void
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picenable(int irq)
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{
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picsetmask(irqmask & ~(1<<irq));
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}
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// Initialize the 8259A interrupt controllers.
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void
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picinit(void)
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{
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// mask all interrupts
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outb(IO_PIC1+1, 0xFF);
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outb(IO_PIC2+1, 0xFF);
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// Set up master (8259A-1)
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// ICW1: 0001g0hi
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// g: 0 = edge triggering, 1 = level triggering
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// h: 0 = cascaded PICs, 1 = master only
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// i: 0 = no ICW4, 1 = ICW4 required
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outb(IO_PIC1, 0x11);
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// ICW2: Vector offset
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outb(IO_PIC1+1, T_IRQ0);
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// ICW3: (master PIC) bit mask of IR lines connected to slaves
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// (slave PIC) 3-bit # of slave's connection to master
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outb(IO_PIC1+1, 1<<IRQ_SLAVE);
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// ICW4: 000nbmap
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// n: 1 = special fully nested mode
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// b: 1 = buffered mode
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// m: 0 = slave PIC, 1 = master PIC
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// (ignored when b is 0, as the master/slave role
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// can be hardwired).
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// a: 1 = Automatic EOI mode
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// p: 0 = MCS-80/85 mode, 1 = intel x86 mode
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outb(IO_PIC1+1, 0x3);
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// Set up slave (8259A-2)
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outb(IO_PIC2, 0x11); // ICW1
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outb(IO_PIC2+1, T_IRQ0 + 8); // ICW2
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outb(IO_PIC2+1, IRQ_SLAVE); // ICW3
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// NB Automatic EOI mode doesn't tend to work on the slave.
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// Linux source code says it's "to be investigated".
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outb(IO_PIC2+1, 0x3); // ICW4
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// OCW3: 0ef01prs
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// ef: 0x = NOP, 10 = clear specific mask, 11 = set specific mask
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// p: 0 = no polling, 1 = polling mode
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// rs: 0x = NOP, 10 = read IRR, 11 = read ISR
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outb(IO_PIC1, 0x68); // clear specific mask
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outb(IO_PIC1, 0x0a); // read IRR by default
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outb(IO_PIC2, 0x68); // OCW3
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outb(IO_PIC2, 0x0a); // OCW3
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if(irqmask != 0xFFFF)
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picsetmask(irqmask);
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}
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